Hi,
Our team is currently working on taping out the "openPulp" design. We have synthesized the design using the Synopsys Design Compiler tool and performed Static Timing Analysis (STA) using Synopsys' Primetime. We noticed some peculiarities in the timing_max_normal_path.rpt report, which can be broadly categorized as follows:
1. Paths from CORE[0].ex_stage to another CORE.id_stage through FPNEW_UNIT, with destination DFF name prefixes typically being mult_dot_op_/, alu_operand_/, or mult_operand_/.
2. Paths from ex_stage to id_stage, with destination DFF name prefixes typically being mult_dot_op_/, alu_operand_/, or mult_operand_/.
3. Paths related to the DFFs with the hwloop_regs_i_hwlp_counter_q_reg_ prefix in the id_stage.
Additionally, we observed that signals such as mult_multicycle_i in the riscv_decoder module are annotated with comments like "//multiplier taking multiple cycles," as well as the apu_singlecycle and apu_multicycle signals.
Our question is: Should the paths mentioned above be treated as multi-cycle paths or false path during synthesis?
We would greatly appreciate any insights or guidance on this matter.
Thank you in advance for your assistance.
Best regards,
[keran]
Our team is currently working on taping out the "openPulp" design. We have synthesized the design using the Synopsys Design Compiler tool and performed Static Timing Analysis (STA) using Synopsys' Primetime. We noticed some peculiarities in the timing_max_normal_path.rpt report, which can be broadly categorized as follows:
1. Paths from CORE[0].ex_stage to another CORE.id_stage through FPNEW_UNIT, with destination DFF name prefixes typically being mult_dot_op_/, alu_operand_/, or mult_operand_/.
2. Paths from ex_stage to id_stage, with destination DFF name prefixes typically being mult_dot_op_/, alu_operand_/, or mult_operand_/.
3. Paths related to the DFFs with the hwloop_regs_i_hwlp_counter_q_reg_ prefix in the id_stage.
Additionally, we observed that signals such as mult_multicycle_i in the riscv_decoder module are annotated with comments like "//multiplier taking multiple cycles," as well as the apu_singlecycle and apu_multicycle signals.
Our question is: Should the paths mentioned above be treated as multi-cycle paths or false path during synthesis?
We would greatly appreciate any insights or guidance on this matter.
Thank you in advance for your assistance.
Best regards,
[keran]