Custom extensions to the RISC-V ISA

[froggyhopper50]

Hello! I'm interested in creating custom extensions to the RISC-V ISA. The goal of these extensions would be to define instructions that perform specific operations (e.g., butterfly operations, twiddle factor generation, modular arithmetic) that I can use to implement various cryptographic primitives (e.g., NTT). I would then like to measure the speedup of these cryptographic primitives with my extensions enabled vs. with my extensions disabled.

What would be the best platform to achieve this goal?

I see one possibility, which is to take the CV32E40P core and extend it with custom functional units using SystemVerilog. I'd then have to find a way to get the compiler to take advantage of the new instructions that I've defined.

While I would be comfortable using SystemVerilog, I'm more interested in exploring the design space of possible instructions rather than attempting to debug a particular hardware design. For this reason, I'm curious if an architectural simulator / instruction set simulator would be more appropriate for my needs. Does PULP offer an architectural simulator / instruction set simulator? I found GVSoC, but I'm not sure if it's what I'm looking for.

Any advice would be greatly appreciated. Thank you!

[kgf]

Hello,

Instruction Set Extensions are one of the most popular things to do with RISC-V. As you point out, it is actually quite tricky, you need to know about the HW and you need to be able to have the tool support. Getting this to work is more complicated than it looks.

Now using an architectural simulator is IMHO not the best way, as these do not really consider the cost of the implementation, and for instruction set extensions, it is usually this cost that is an issue. On an architectural simulator you can conjure up a super instruction, but it may be too costly to implement (either in execution time, or implementation area) and it might not be as good as it seems.

Usually to develop good extensions, you need to understand the limitations of the current implementation, and examine optimized code to see where you are loosing (in terms of cycles) and see what can be done. Note that the same effort is also needed to see if the compilers are able to generate good code. I think this sort of manual inspection is very important to understand the issues of the current system. This can be made with architectural simulators.

As for the cores.. CV32E40P has actually many many extensions included. So the extension space is a bit limited. As a 4 stage pipelined core, it is also a bit tricky with all the tricks in the pipeline fwds etc to untangle.. Ibex would be a simpler core to play with..

If you are less into HW, and more at home with Scale like languages, VexRiscV from Charles Pappon might actually be what you are looking for:
https://github.com/SpinalHDL/VexRiscv

Hope that helps,
KGF