[Vivado] behavioural simulation won't start

[andrea.spitale]

Hi there!
I'm posting here as I am having some trouble with setting up PULPissimo to be behaviourally simulated (i.e. pre synthesis) on Vivado. In order to do so, I've cloned the PULPissimo repository, then run the update ips script and finally loaded all files from ips and rtl folders into vivado project. I'll list the issues I've encountered, together with vivado logs describing the errors and warning the software detected, considering I am running a fully licensed 2020.2 version under Linux.

1) i've a huge issue with "include" files, that is the files referred by `include directives. The vivado log referring to this issue is the one named "vivado_include.log".
1.1) Initially I managed to fix some of these errors by adding the paths to the folders containing those files in "Verilog Include Files Search Paths", which is a setting that can be found by going through Project Manager -> Settings -> General(and Simulation) -> Verilog Options, but this means adding one path for every "include" error the compiler detects, so it requires a lot of work. Moreover it doesn't seem to be always working, as it didn't fix the problem when I created a new project and the log content was the same as "vivado_include.log".

2) I created another project, this time copying and including all .sv, .svh, .v files from ips and rtl PULPissimo folders, so all files are in the same folder. I had to modify the `include directives of "fpnew" IP files in order to have correct `include paths. Moreover I had to comment out the "`ifdef synthesis" directive in hwpe_ctrl_interfaces.sv, as the compiler was not able to recognize "timeunit" and "timeprecision" keywords, although it should. Then, using xilinx related scripts inside "fpga/zcu102" folder as a guideline, I created the Xilinx IPs PULPissimo requires, that is two BRAMs and two clock generators, named xilinx_clk_mngr, xilinx_slow_clk_mngr, xilinx_private_ram and xilinx_interleaved_ram. Once I ran the behavioural simulation process, the compile phase went fine, but then the elaborate one was stopped with errors listed in "vivado_elaborate.log" file. I have to say I also read some warnings during compile phase, which details are again listed in "vivado_elaborate.log".

3) I created a new project, importing all files from ip and rtl folders. I've set some of the files referred by `include directives as "verilog header" from the files properties. Then I copied the registers.svh file inside "common_cells" folder of FPNEW ip, as the compiler was not able to find it. Moreover I had to comment out the "`ifdef synthesis" directive in hwpe_ctrl_interfaces.sv. However I still encountered errors after running behavioural simulation process, one of them referring to file riscv_alu.sv, with compiler indicating that  "riscv_defines" packanot being declared.ge has not been declared. The log of this operation is inside "vivado_third_attempt.log".

All .log files are inside the attached "vivado_error_logs.zip" file.

Hope everything is clear. Thank you for your time!

[meggiman]

Hi there!
I'm posting here as I am having some trouble with setting up PULPissimo to be behaviourally simulated (i.e. pre synthesis) on Vivado. In order to do so, I've cloned the PULPissimo repository, then run the update ips script and finally loaded all files from ips and rtl folders into vivado project. I'll list the issues I've encountered, together with vivado logs describing the errors and warning the software detected, considering I am running a fully licensed 2020.2 version under Linux.

1) i've a huge issue with "include" files, that is the files referred by `include directives. The vivado log referring to this issue is the one named "vivado_include.log".
1.1) Initially I managed to fix some of these errors by adding the paths to the folders containing those files in "Verilog Include Files Search Paths", which is a setting that can be found by going through Project Manager -> Settings -> General(and Simulation) -> Verilog Options, but this means adding one path for every "include" error the compiler detects, so it requires a lot of work. Moreover it doesn't seem to be always working, as it didn't fix the problem when I created a new project and the log content was the same as "vivado_include.log".

2) I created another project, this time copying and including all .sv, .svh, .v files from ips and rtl PULPissimo folders, so all files are in the same folder. I had to modify the `include directives of "fpnew" IP files in order to have correct `include paths. Moreover I had to comment out the "`ifdef synthesis" directive in hwpe_ctrl_interfaces.sv, as the compiler was not able to recognize "timeunit" and "timeprecision" keywords, although it should. Then, using xilinx related scripts inside "fpga/zcu102" folder as a guideline, I created the Xilinx IPs PULPissimo requires, that is two BRAMs and two clock generators, named xilinx_clk_mngr, xilinx_slow_clk_mngr, xilinx_private_ram and xilinx_interleaved_ram. Once I ran the behavioural simulation process, the compile phase went fine, but then the elaborate one was stopped with errors listed in "vivado_elaborate.log" file. I have to say I also read some warnings during compile phase, which details are again listed in "vivado_elaborate.log".

3) I created a new project, importing all files from ip and rtl folders. I've set some of the files referred by `include directives as "verilog header" from the files properties. Then I copied the registers.svh file inside "common_cells" folder of FPNEW ip, as the compiler was not able to find it. Moreover I had to comment out the "`ifdef synthesis" directive in hwpe_ctrl_interfaces.sv. However I still encountered errors after running behavioural simulation process, one of them referring to file riscv_alu.sv, with compiler indicating that  "riscv_defines" packanot being declared.ge has not been declared. The log of this operation is inside "vivado_third_attempt.log".

All .log files are inside the attached "vivado_error_logs.zip" file.

Hope everything is clear. Thank you for your time!

Hi Andrea,

There are already working FPGA ports for many FPGA boards availabe in the repository. Instead of trying to manually add all files to the projects, you should do it the same way as the existing ports handle this: They source a couple of autogenerated (as a side-effect of ./update-ips or ./generate-scripts) tcl scripts in fpga/pulpissimo/tcl that contain the correct paths and include paths for the whole project. Trying to do this manually is extremely error-prone and should be avoided. If your goal is to port PULPissimo to a new fpga board I would suggest you to copy one of the existing board specific subdirectories in the fpga folder (e.g. pulpissimo-genesys2) and start from there. However, I never tried to simulate the RTL with Vivado since we normally use a dedicated RTL simulator (Mentor Questasim) to do this. So if we really want to use Vivado for simulation you will have to modify the existing scripts to also add some testbench environment to vivado. The relevant verification source code we usually use with Questasim you can find in rtl/tb. However, I have some doubts that this code will work in Vivado straight out-of-the-box so you probably have to manually modify a couple of things.

Best,
Manuel

[andrea.spitale]

Hi Manuel,

thank you for your response. Ye, I didn't see there were scripts for the ZCU 102 board, my bad. So I used the provided makefile, but I get the following errors in vivado as soon as the process seems to finish:

Code:

ERROR: [Synth 8-1587] an enum variable may only be assigned to same enum typed variable or one of its values [/home/spitale/PULPissimo_git/ips/riscv/rtl/riscv_ex_stage.sv:445]
INFO: [Synth 8-2350] module riscv_ex_stage ignored due to previous errors [/home/spitale/PULPissimo_git/ips/riscv/rtl/riscv_ex_stage.sv:40]
Failed to read verilog '/home/spitale/PULPissimo_git/ips/riscv/rtl/riscv_ex_stage.sv'
2 Infos, 8 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details

any suggestion?

[andrea.spitale]

Hi Manuel,

thank you for your response. Ye, I didn't see there were scripts for the ZCU 102 board, my bad. So I used the provided makefile, but I get the following errors in vivado as soon as the process seems to finish:

Code:

ERROR: [Synth 8-1587] an enum variable may only be assigned to same enum typed variable or one of its values [/home/spitale/PULPissimo_git/ips/riscv/rtl/riscv_ex_stage.sv:445]
INFO: [Synth 8-2350] module riscv_ex_stage ignored due to previous errors [/home/spitale/PULPissimo_git/ips/riscv/rtl/riscv_ex_stage.sv:40]
Failed to read verilog '/home/spitale/PULPissimo_git/ips/riscv/rtl/riscv_ex_stage.sv'
2 Infos, 8 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details

any suggestion?

Anyone has any clue? Am I doing something wrong?

[LarsKeuninckx]

I have exactly the same problem, when compiling for the nexysA7-100T board:

Use nexys4DDR/A7 constraints.
# synth_design -rtl -name rtl_1 -sfcu;
Command: synth_design -rtl -name rtl_1 -sfcu
Starting synth_design
Using part: xc7a100tcsg324-1
Top: xilinx_pulpissimo
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
WARNING: [Synth 8-1921] elaboration system task error violates IEEE 1800 syntax [/home/lars/Argus/pulpissimo/ips/pulp_soc/rtl/components/apb_soc_ctrl.sv:137]
WARNING: [Synth 8-2507] parameter declaration becomes local in hwpe_stream_merge with formal parameter declaration list [/home/lars/Argus/pulpissimo/ips/hwpe-stream/rtl/hwpe_stream_merge.sv:31]
WARNING: [Synth 8-2507] parameter declaration becomes local in hwpe_stream_split with formal parameter declaration list [/home/lars/Argus/pulpissimo/ips/hwpe-stream/rtl/hwpe_stream_split.sv:31]
WARNING: [Synth 8-2507] parameter declaration becomes local in hwpe_stream_split with formal parameter declaration list [/home/lars/Argus/pulpissimo/ips/hwpe-stream/rtl/hwpe_stream_split.sv:32]
WARNING: [Synth 8-1921] elaboration system task error violates IEEE 1800 syntax [/home/lars/Argus/pulpissimo/ips/pulp_soc/rtl/pulp_soc/interleaved_crossbar.sv:48]
WARNING: [Synth 8-1921] elaboration system task error violates IEEE 1800 syntax [/home/lars/Argus/pulpissimo/rtl/pulpissimo/pad_control.sv:197]
WARNING: [Synth 8-1921] elaboration system task error violates IEEE 1800 syntax [/home/lars/Argus/pulpissimo/rtl/pulpissimo/pad_control.sv:198]
WARNING: [Synth 8-1921] elaboration system task error violates IEEE 1800 syntax [/home/lars/Argus/pulpissimo/rtl/pulpissimo/pad_control.sv:199]
WARNING: [Synth 8-2490] overwriting previous definition of module pulp_clock_mux2 [/home/lars/Argus/pulpissimo/ips/tech_cells_generic/src/deprecated/pulp_clk_cells_xilinx.sv:53]
WARNING: [Synth 8-2490] overwriting previous definition of module pulp_clock_gating [/home/lars/Argus/pulpissimo/fpga/pulpissimo-nexys/rtl/pulp_clock_gating_xilinx.sv:11]
ERROR: [Synth 8-1587] an enum variable may only be assigned to same enum typed variable or one of its values [/home/lars/Argus/pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv:445]
INFO: [Synth 8-2350] module riscv_ex_stage ignored due to previous errors [/home/lars/Argus/pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv:40]
Failed to read verilog '/home/lars/Argus/pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv'
2 Infos, 10 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details
INFO: [Common 17-206] Exiting Vivado at Wed Jan 6 11:08:05 2021...
Makefile:11: recipe for target 'all' failed
make[1]: *** [all] Error 1
make[1]: Leaving directory '/home/lars/Argus/pulpissimo/fpga/pulpissimo-nexys'
Makefile:41: recipe for target 'nexys' failed

Does anyone know how to solve this?

[LarsKeuninckx]

I found a way around this, but it is messy and not sure what other problems this causes. In the offending file pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv, change line 445 from:

'{default: C_DIV}, // DIVSQRT
to:
'{default: fpnew_pkg::MERGED}, // DIVSQRT

As far as I can tell (?) this is related to the instantation of the FP unit. Note that the error described above happened even when synthesis is done for the (non-FP) Ibex core, as described by taking the 'Core Selection' steps in https://github.com/pulp-platform/pulpiss...l-platform.

Possibly, the version of Vivado is causing this error. As described in the README.md, Vivado v2018.3 was used. Whereas, the error appeared for me with Vivado v2020.1.

[andrea.spitale]

I found a way around this, but it is messy and not sure what other problems this causes. In the offending file pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv, change line 445 from:

     '{default: C_DIV}, // DIVSQRT
to:
     '{default: fpnew_pkg::MERGED}, // DIVSQRT

As far as I can tell (?) this is related to the instantation of the FP unit. Note that the error described above happened even when synthesis is done for the (non-FP) Ibex core, as described by taking the 'Core Selection' steps in https://github.com/pulp-platform/pulpiss...l-platform.

Possibly, the version of Vivado is causing this error. As described in the README.md, Vivado v2018.3 was used. Whereas, the error appeared for me with Vivado v2020.1.

Hi, Thank you for sharing your experience! I am using vivado 2020.1 as well. Did you find any other error after changing that line?

[LarsKeuninckx]

I found a way around this, but it is messy and not sure what other problems this causes. In the offending file pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv, change line 445 from:

     '{default: C_DIV}, // DIVSQRT
to:
     '{default: fpnew_pkg::MERGED}, // DIVSQRT

As far as I can tell (?) this is related to the instantation of the FP unit. Note that the error described above happened even when synthesis is done for the (non-FP) Ibex core, as described by taking the 'Core Selection' steps in https://github.com/pulp-platform/pulpiss...l-platform.

Possibly, the version of Vivado is causing this error. As described in the README.md, Vivado v2018.3 was used. Whereas, the error appeared for me with Vivado v2020.1.

Hi, Thank you for sharing your experience! I am using vivado 2020.1 as well. Did you find any other error after changing that line?

You're welcome. After changing above line, it compiled without error, resulting in .bit and .bin files. Now I am trying to make it work for the Digilent ARTY-A7-100T board, as that is the board I have.