Cheshire with two cores

[kgf]

I am guessing that some of the additions proved a bit too much for the timing constraints. You could (in most cases) relax the constraints to get through it. Note that for most PULP IP, the code is not FPGA optimized, we use FPGAs for emulation and not as the primary target. That is why, the speed at which it works is not much of an issue. Our usual targets are ASIC designs where the optimizations may differ quite a bit from FPGAs (due to internal resources like BRAMs, DSPs etc).

Of course it is not like the timing contraints should go from 50ns to 5000ns.. that could point out to an issue somewhere