some questions about pulpissimo L1 memory

[jsen_che11]

1. I think I’ve figured out some of it. In the diagram on the left, I$ / Ibuf refers to the traditional instruction cache, while the data cache is not shown because it’s just a single-cycle register.
   
2. Unlike Pulpissimo, does the multicore system on the right have a dedicated data cache (TCDM) and instruction cache, and do these two then exchange data with the L2 cache via the SoC bus? Is my understanding correct?
   Is my current understanding correct?  sincerely hope to receive your response.