01-02-2025, 02:23 PM
Hello,
Please note that PULP is not a single architecture, it is a series of building blocks we use to design novel computing architectures. So there is not one PULP, there are independent projects underneath it. We have developed different RISC-V cores:
- Ariane (now CVA6 by OpenHW)
- RI5CY (now CV32E40P by OpenHW)
- Zeroriscy (now Ibex by LowRISC)
- Snitch
And combined them to get single microcontrollers (PULPinio PULPissimo, Cheshire), many-core accelerators (Snitch clusters, PULP clusters), and largers systems (Mempool, Occamy)
Since I get this question a lot, we do not really have a traditional multi-core system (with the exception of Culsans https://github.com/pulp-platform/culsans), our many-core architectures are geared towards data centric applications and used shared scratchpad memories and not traditional caches.
We use the public git repositories for our work, so all of them are actually up to date, but some are no longer an active research area for us (i.e. we achieved what we set out to do), and some yu need to check the development branches.
In most cases, we use Siemens/Mentor Questasim, any recent version should do the trick. Notice that the Intel/Altera edition is not really 100% the same as the regular Questasim, so it may not simulate properly. We have been moving towards using Verilator for most of our projects, but there is a lot of code, and not all of them have been yet converted.
Commercial EDA vendors (so far) do not really allow us to publish the synthesis and PR scripts. For the open source versions (https://github.com/pulp-platform/cheshire-ihp130-o) everything is available
Benchmarks are usually project specific, i.e. you need to have your application that you consider running on your system.
SDK is again a complicated issue, different platforms have variations of the system. Check for example Deeploy https://github.com/pulp-platform/Deeploy for a system we are currently using.
Technology specific aspects like PLLs and I/O cells will need to be managed by you, we are not allowed to make these public.
I hope this helps a bit,
Happy New Year
KGF
Please note that PULP is not a single architecture, it is a series of building blocks we use to design novel computing architectures. So there is not one PULP, there are independent projects underneath it. We have developed different RISC-V cores:
- Ariane (now CVA6 by OpenHW)
- RI5CY (now CV32E40P by OpenHW)
- Zeroriscy (now Ibex by LowRISC)
- Snitch
And combined them to get single microcontrollers (PULPinio PULPissimo, Cheshire), many-core accelerators (Snitch clusters, PULP clusters), and largers systems (Mempool, Occamy)
Since I get this question a lot, we do not really have a traditional multi-core system (with the exception of Culsans https://github.com/pulp-platform/culsans), our many-core architectures are geared towards data centric applications and used shared scratchpad memories and not traditional caches.
We use the public git repositories for our work, so all of them are actually up to date, but some are no longer an active research area for us (i.e. we achieved what we set out to do), and some yu need to check the development branches.
In most cases, we use Siemens/Mentor Questasim, any recent version should do the trick. Notice that the Intel/Altera edition is not really 100% the same as the regular Questasim, so it may not simulate properly. We have been moving towards using Verilator for most of our projects, but there is a lot of code, and not all of them have been yet converted.
Commercial EDA vendors (so far) do not really allow us to publish the synthesis and PR scripts. For the open source versions (https://github.com/pulp-platform/cheshire-ihp130-o) everything is available
Benchmarks are usually project specific, i.e. you need to have your application that you consider running on your system.
SDK is again a complicated issue, different platforms have variations of the system. Check for example Deeploy https://github.com/pulp-platform/Deeploy for a system we are currently using.
Technology specific aspects like PLLs and I/O cells will need to be managed by you, we are not allowed to make these public.
I hope this helps a bit,
Happy New Year
KGF
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