03-25-2025, 09:30 AM
Hi, thanks for the fast and helpful reply!
Following the step by step tutorial I have been able to simulate the "Hello !" example on QuestaSim! However, compiling and running applications on the FPGA (Zedboard) with Pulpissimo is a requirement for an undergraduate research project which I am currently taking part of, so I need to go further. In the step by step tutorial, the use Pulpissimo's v7.0.0 release is instructed (git checkout v7.0.0), since that is the release "which supports working with pulp-sdk", but over at https://github.com/pulp-platform/pulpissimo/releases/tag/v7.0.0 , it is stated that support for Xilinx Zedboard is removed, due to Zedboard's lack of space to fit the Pulpissimo design. It is also said that "the bitstream generation flow will fail due to insuffienct LUTs available", statement which I guess I have empirically verified.
Because of that, I have tried to use Pulpissimo's v6.0.0 release, since it is my goal to work with the Zedboard. I have, then, been able to build pulp-sdk, generate the bitstream for Pulpissimo and flash it to the Zedboard without errors. However, I am unable to set and use OpenOCD as instructed on Pulpissimo's v6.0.0 ReadMe file. I am citing my commands and the error that I can't still make sense of:
That last command gives me the following error:
Then, I have tried to use Pulpissimo v7.0.0 to compile OpenOCD (but doing git checkout v7.0.0 this time) and got the same error:
I was wondering if you could enlighten me regarding this problem. Maybe there is some misconception on my behalf about the process to compile OpenOCD, but I am not sure if it is possible to use it to load binaries into Pulpissimo v6.0.0 on the Zedboard.
Thank you again for your attention!
Following the step by step tutorial I have been able to simulate the "Hello !" example on QuestaSim! However, compiling and running applications on the FPGA (Zedboard) with Pulpissimo is a requirement for an undergraduate research project which I am currently taking part of, so I need to go further. In the step by step tutorial, the use Pulpissimo's v7.0.0 release is instructed (git checkout v7.0.0), since that is the release "which supports working with pulp-sdk", but over at https://github.com/pulp-platform/pulpissimo/releases/tag/v7.0.0 , it is stated that support for Xilinx Zedboard is removed, due to Zedboard's lack of space to fit the Pulpissimo design. It is also said that "the bitstream generation flow will fail due to insuffienct LUTs available", statement which I guess I have empirically verified.
Code:
53 Infos, 54 Warnings, 6 Critical Warnings and 3 Errors encountered.
place_design failed
ERROR: [Common 17-69] Command failed: Placer could not place all instances
INFO: [Common 17-206] Exiting Vivado at Mon Mar 24 15:49:00 2025...
[Mon Mar 24 15:49:01 2025] impl_1 finished
# open_run impl_1
ERROR: [Common 17-69] Command failed: Run 'impl_1' failed. Unable to open
INFO: [Common 17-206] Exiting Vivado at Mon Mar 24 15:49:01 2025...
Makefile:14: recipe for target 'all' failed
make[1]: *** [all] Error 1
make[1]: Leaving directory '/home/victor/pulp_box/pulpissimo/fpga/pulpissimo-zedboard'
Makefile:53: recipe for target 'zedboard' failed
make: *** [zedboard] Error 2Because of that, I have tried to use Pulpissimo's v6.0.0 release, since it is my goal to work with the Zedboard. I have, then, been able to build pulp-sdk, generate the bitstream for Pulpissimo and flash it to the Zedboard without errors. However, I am unable to set and use OpenOCD as instructed on Pulpissimo's v6.0.0 ReadMe file. I am citing my commands and the error that I can't still make sense of:
- cd pulpissimo
- git checkout v6.0.0
- make build-pulp-sdk
- source env/pulpissimo.sh
- make checkout (after that, I modified the rtl_vopt.tcl as suggested on the guide just regarding QuestaSim compatibility)
- make build
- cd ~/pulp_box/pulpissimo
- ./update-ips
- cd fpga
- make zedboard (then, flashed the bitstream to the FPGA without erros)
- cd ../pulp-sdk
- source configs/pulpissimo.sh
- source configs/fpgas/pulpissimo/genesys2.sh
- make clean all (after that, I have installed all required dependencies for OpenOCD compilation)
- source sourceme.sh && ./pulp-tools/bin/plpbuild checkout build --p openocd --stdout
- export OPENOCD=~/pulp_box/pulpissimo/pulp-sdk/pkg/openocd/1.0
- $OPENOCD/bin/openocd -f ~/pulp_box/pulpissimo/fpga/pulpissimo-zedboard/openocd-zedboard-hs2.cfg
That last command gives me the following error:
Code:
Open On-Chip Debugger 0.10.0+dev-00615-g53a17c1bb (2025-03-24-17:22)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
none separate
adapter speed: 1000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
TapName Enabled IdCode Expected IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
0 riscv.unknown0 Y 0x00000000 0x10102001 5 0x01 0x03
1 riscv.cpu Y 0x00000000 0x249511c3 5 0x01 0x03
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.unknown0 tap/device found: 0x03727093 (mfg: 0x049 (Xilinx), part: 0x3727, ver: 0x0)
Warn : JTAG tap: riscv.unknown0 UNEXPECTED: 0x03727093 (mfg: 0x049 (Xilinx), part: 0x3727, ver: 0x0)
Error: JTAG tap: riscv.unknown0 expected 1 of 1: 0x10102001 (mfg: 0x000 (<invalid>), part: 0x0102, ver: 0x1)
Info : JTAG tap: riscv.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4)
Warn : JTAG tap: riscv.cpu UNEXPECTED: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4)
Error: JTAG tap: riscv.cpu expected 1 of 1: 0x249511c3 (mfg: 0x0e1 (Wintec Industries), part: 0x4951, ver: 0x2)
Error: Trying to use configured scan chain anyway...
Error: riscv.cpu: IR capture error; saw 0x03 not 0x01
Warn : Bypassing JTAG setup events due to errors
openocd: src/target/riscv/riscv.c:2366: riscv_xlen_of_hart: Assertion `r->xlen[hartid] != -1' failed.
Aborted (core dumped)Then, I have tried to use Pulpissimo v7.0.0 to compile OpenOCD (but doing git checkout v7.0.0 this time) and got the same error:
Code:
Open On-Chip Debugger 0.10.0+dev-00615-g2785f0f5c (2025-03-24-18:06)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
none separate
adapter speed: 1000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
TapName Enabled IdCode Expected IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
0 riscv.unknown0 Y 0x00000000 0x10102001 5 0x01 0x03
1 riscv.cpu Y 0x00000000 0x249511c3 5 0x01 0x03
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.unknown0 tap/device found: 0x03727093 (mfg: 0x049 (Xilinx), part: 0x3727, ver: 0x0)
Warn : JTAG tap: riscv.unknown0 UNEXPECTED: 0x03727093 (mfg: 0x049 (Xilinx), part: 0x3727, ver: 0x0)
Error: JTAG tap: riscv.unknown0 expected 1 of 1: 0x10102001 (mfg: 0x000 (<invalid>), part: 0x0102, ver: 0x1)
Info : JTAG tap: riscv.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4)
Warn : JTAG tap: riscv.cpu UNEXPECTED: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4)
Error: JTAG tap: riscv.cpu expected 1 of 1: 0x249511c3 (mfg: 0x0e1 (Wintec Industries), part: 0x4951, ver: 0x2)
Error: Trying to use configured scan chain anyway...
Error: riscv.cpu: IR capture error; saw 0x03 not 0x01
Warn : Bypassing JTAG setup events due to errors
openocd: src/target/riscv/riscv.c:2366: riscv_xlen_of_hart: Assertion `r->xlen[hartid] != -1' failed.
Aborted (core dumped)I was wondering if you could enlighten me regarding this problem. Maybe there is some misconception on my behalf about the process to compile OpenOCD, but I am not sure if it is possible to use it to load binaries into Pulpissimo v6.0.0 on the Zedboard.
Thank you again for your attention!