Today, 09:17 AM
(10-30-2024, 06:26 AM)andlo47 Wrote: Hi all, Speed Stars Online
I'm trying to generate a bit file for Cheshire v0.1.0 with two cores for the Genesys2 board using Vivado 2023.2, but get an error stating that timing constraints are not met.
I can generate the bit file from an earlier commit, f316617, of the Cheshire repo. I did remove the USB support as it would not fit on the FPGA of Genesys2.
I'm quite new to this and would appreciate any help. I'm not sure where to start looking.
Regards,
/Andreas
Does Cheshire v0.1.0 officially support dual-core configurations on the Genesys2, or are you modifying it manually?