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Synthesis 8 core pulp for ASIC
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02-28-2019, 07:00 AM
(This post was last modified: 02-28-2019, 07:01 AM by TerryLewis.
Edit Reason: typos
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Is it possible to generate a netlist using Design Compiler? Is there a sample of something? I'm not a tech guy. Just searching for some tutorials.
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Synthesis 8 core pulp for ASIC - by Athena - 02-11-2019, 04:41 PM
RE: Synthesis 8 core pulp for ASIC - by kgf - 02-11-2019, 05:11 PM
RE: Synthesis 8 core pulp for ASIC - by TerryLewis - 02-28-2019, 07:00 AM
RE: Synthesis 8 core pulp for ASIC - by kgf - 02-28-2019, 07:08 AM
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