05-08-2019, 07:41 AM
Hello,
I am trying to write and read L2 memory via JTAG . According to datasheet memory map it should be in 0x1c000000...0x1c080000. and in soc_bus_defines there is definition
// MASTER PORT TO L2
`define SOC_L2_START_ADDR 32'h1C00_0000
`define SOC_L2_END_ADDR 32'h1FFF_FFFF
However the above parameters are not used anywhere and I can not succesfully write and read to that area. I get always zeros from any memory address that i have tried.
So where is the memory located actually ?
I went through the related RTL codes and found local parameter TCDM_START_ADDRESS, which is set to diffrent memory area, and it looked that might be the used area but still the memory access is not working.
As background:
I have succesfylly read and written quite a many peripheral resister, SOC control registers etc, so the JTAG link as such works.
I have implemented Pulpissomo on KIntex FPGA on Genesys board. The xilinx memories seem to be in shape.
Regards, skor
I am trying to write and read L2 memory via JTAG . According to datasheet memory map it should be in 0x1c000000...0x1c080000. and in soc_bus_defines there is definition
// MASTER PORT TO L2
`define SOC_L2_START_ADDR 32'h1C00_0000
`define SOC_L2_END_ADDR 32'h1FFF_FFFF
However the above parameters are not used anywhere and I can not succesfully write and read to that area. I get always zeros from any memory address that i have tried.
So where is the memory located actually ?
I went through the related RTL codes and found local parameter TCDM_START_ADDRESS, which is set to diffrent memory area, and it looked that might be the used area but still the memory access is not working.
As background:
I have succesfylly read and written quite a many peripheral resister, SOC control registers etc, so the JTAG link as such works.
I have implemented Pulpissomo on KIntex FPGA on Genesys board. The xilinx memories seem to be in shape.
Regards, skor