Pulpissimo bitstream generation.

[meggiman]

Hey,

I am stuck also at that error " openocd: src/target/riscv/riscv.c:2530: riscv_set_current_hartid: Assertion `riscv_hart_enabled(target, hartid)' failed. ", I've read the comments but I couldn't locate that patched openocd that comes with the SDK. May you please elaborate more one this  ?

Thanks !

Hi AhmedZaky,

I just realized that the patched Openocd is not installed by default if you do not have access to the artifactory server (file server at ETH that contains precompiled binaries). However 
I revised the README in the fpga branch and added some sections on how to install the patched OpenOCD from source. Please follow the instructions at https://github.com/pulp-platform/pulpiss...nd-openocd.

Hey Thanks for your reply, I already applied the patch manually to the source file of openocd and it works. 

Noe wen I try to either run the example the FPGA or trying to debug I got the following errors: 

1- When I am trying to run the example directly without debugging using the " make run" command: 


"/pulp-sdk/pkg/sdk/dev/install/ws/python/runner/fpga/pulpissimo/elf_run.gdb:1: Error in sourced command file:  localhost:3333: Connection timed out" 

2- when I try to use the debugger by running three terminals at the same time " openocd, GDB and screen / minicom" I face the following issue: 

            - Minicom: I receive nothing from minicom, and I am assigning the right USB port hopefully. 
            - Screen: I receive odd characters instead of the real message. 

Could you please help on that ? What might be the problem ? 

Thanks so much !

Unless you connected the second micro-USB cable for the UART to the wrong connector on the Genesys2 board the most likely reason is that you set the wrong frequency (or even forgot to specify it at all) for the core and peripheral clock in your application which results in a different baudrate (see FPGA section in README). The default frequency currently mentioned in the README relates to the most recent version of PULPissimo. Depending at which commit you generated the bitstream the frequency might be a different one since I only recently changed them to higher values (the mentioned 40 MHz and 20 MHz). You can either pull the latest commits on the FPGA branch and regenerate the bitstream or check the timing summary in vivado to figure out which frequencies are actually used with your current bitstream. In any case you must set the frequency in your application since at the moment the SDK does not assume any reasonable defaults (most likely we will change that in the future).  

Regarding the 'make run' target: The runner script for the FPGA is still unstable and occasionally does not work due to timing problems when starting the OpenOCD server, gdb and the minicom session. For the moment I recommend to use OpenOCD and gdb manually as documented in the first part of the README. This approach so far worked reliably for me and has the additional benefit that you can debug your application or even the runtime initialization before entering main() with gdb.