10-22-2019, 08:19 AM
Hello.
In Pulpissimo, there are 2 JTAG modules - dmi_jtag, dm_top / jtag_tap_top & lint_jtag_wrap (pulp_soc.sv).
I guess dmi_jtag & dm_top are from RISC-V Debug Specification,
and jtag_tap_top & lint_jtag_wrap are sub-module of adv_dbg_if.
In Pulpino, zero-riscy core, whose registers are memory-mapped, uses adv_dbg_if as a debug module.
But ibex core at Pulpissimo follows the RISC-V Debug Specification and has no debug interface except one bit debug signal.
So, I don't know why lint_jtag_wrap still necessary in Pulpissimo.
(Any limitations for dm_top to access system bus ??)
Thanks.
In Pulpissimo, there are 2 JTAG modules - dmi_jtag, dm_top / jtag_tap_top & lint_jtag_wrap (pulp_soc.sv).
I guess dmi_jtag & dm_top are from RISC-V Debug Specification,
and jtag_tap_top & lint_jtag_wrap are sub-module of adv_dbg_if.
In Pulpino, zero-riscy core, whose registers are memory-mapped, uses adv_dbg_if as a debug module.
But ibex core at Pulpissimo follows the RISC-V Debug Specification and has no debug interface except one bit debug signal.
So, I don't know why lint_jtag_wrap still necessary in Pulpissimo.
(Any limitations for dm_top to access system bus ??)
Thanks.