Are you running this with the mhartid set to 0? If not, do you use openocd master (atleast with this patch https://github.com/riscv/riscv-openocd/c...52438fec6a).
Regarding the instruction decode error, what is your output of "riscv32-unknown-elf-gcc --verbose --version"?
Unfortunately I don't have a zedboard so I can't really help you debug. Internally we use genesys2 and the other FPGA ports are contributions, which besides running synthesis I can't verify.
Regarding the instruction decode error, what is your output of "riscv32-unknown-elf-gcc --verbose --version"?
Unfortunately I don't have a zedboard so I can't really help you debug. Internally we use genesys2 and the other FPGA ports are contributions, which besides running synthesis I can't verify.