PULPissimo FLL bypass

[heavySea]

Hello Supra,

I removed the FLLs and instead used something like the following to propagate the clocks  in soc_clk_rst_gen.sv

Code:

            //SoC Clock
        assign s_clk_fll_soc = ref_clk_i;
           assign s_clk_soc = s_clk_fll_soc;
           assign soc_fll_slave_r_data_o = 'b0;
           assign soc_fll_slave_ack_o = 1'b1;
           assign soc_fll_slave_lock_o = 1'b1;

You are on the right track. Technically you do not need the FLL Bus Interface, since you do not have the FLLs.
But you should make sure, that the clocks are not active during resets, e.g. by

Code:

assign s_clk_soc = ref_clk_i & rstn_glob_i;

But my simulation gets stuck at "Waiting for  end of computation".

Have you checked, if the core or any peripheral is still doing something? What program did you run? How does it print it's outputs? stdout or UART?


For case 3:

Separate clocks for soc and jtag in test bench

You don't need an additional clock for JTAG, since there is already one.
But you might want to have a separate clocks for SoC/CPU and peripherals (like there are two FLL's in the original design)

Code:

I introduced a new net to distribute a faster clock to tmp_clk_ref when JTAG is not in action.

It should not matter if JTAG is in action. Where does temp_clk_ref source from? What does it drive?

This time too I get stuck at "Waiting for  end of computation". The change to soc_clk_rst_gen.sv is same as in case 2.

Then have a look at the core where it gets stuck. The program counter would be a good start to look at.
Just out of curiosity, which core are you using? Ibex or Riscy?

Cheers