12-10-2020, 11:14 AM
(This post was last modified: 12-10-2020, 11:16 AM by andrea.spitale.)
Hi there!
I'm posting here as I am having some trouble with setting up PULPissimo to be behaviourally simulated (i.e. pre synthesis) on Vivado. In order to do so, I've cloned the PULPissimo repository, then run the update ips script and finally loaded all files from ips and rtl folders into vivado project. I'll list the issues I've encountered, together with vivado logs describing the errors and warning the software detected, considering I am running a fully licensed 2020.2 version under Linux.
1) i've a huge issue with "include" files, that is the files referred by `include directives. The vivado log referring to this issue is the one named "vivado_include.log".
1.1) Initially I managed to fix some of these errors by adding the paths to the folders containing those files in "Verilog Include Files Search Paths", which is a setting that can be found by going through Project Manager -> Settings -> General(and Simulation) -> Verilog Options, but this means adding one path for every "include" error the compiler detects, so it requires a lot of work. Moreover it doesn't seem to be always working, as it didn't fix the problem when I created a new project and the log content was the same as "vivado_include.log".
2) I created another project, this time copying and including all .sv, .svh, .v files from ips and rtl PULPissimo folders, so all files are in the same folder. I had to modify the `include directives of "fpnew" IP files in order to have correct `include paths. Moreover I had to comment out the "`ifdef synthesis" directive in hwpe_ctrl_interfaces.sv, as the compiler was not able to recognize "timeunit" and "timeprecision" keywords, although it should. Then, using xilinx related scripts inside "fpga/zcu102" folder as a guideline, I created the Xilinx IPs PULPissimo requires, that is two BRAMs and two clock generators, named xilinx_clk_mngr, xilinx_slow_clk_mngr, xilinx_private_ram and xilinx_interleaved_ram. Once I ran the behavioural simulation process, the compile phase went fine, but then the elaborate one was stopped with errors listed in "vivado_elaborate.log" file. I have to say I also read some warnings during compile phase, which details are again listed in "vivado_elaborate.log".
3) I created a new project, importing all files from ip and rtl folders. I've set some of the files referred by `include directives as "verilog header" from the files properties. Then I copied the registers.svh file inside "common_cells" folder of FPNEW ip, as the compiler was not able to find it. Moreover I had to comment out the "`ifdef synthesis" directive in hwpe_ctrl_interfaces.sv. However I still encountered errors after running behavioural simulation process, one of them referring to file riscv_alu.sv, with compiler indicating that "riscv_defines" packanot being declared.ge has not been declared. The log of this operation is inside "vivado_third_attempt.log".
All .log files are inside the attached "vivado_error_logs.zip" file.
Hope everything is clear. Thank you for your time!
I'm posting here as I am having some trouble with setting up PULPissimo to be behaviourally simulated (i.e. pre synthesis) on Vivado. In order to do so, I've cloned the PULPissimo repository, then run the update ips script and finally loaded all files from ips and rtl folders into vivado project. I'll list the issues I've encountered, together with vivado logs describing the errors and warning the software detected, considering I am running a fully licensed 2020.2 version under Linux.
1) i've a huge issue with "include" files, that is the files referred by `include directives. The vivado log referring to this issue is the one named "vivado_include.log".
1.1) Initially I managed to fix some of these errors by adding the paths to the folders containing those files in "Verilog Include Files Search Paths", which is a setting that can be found by going through Project Manager -> Settings -> General(and Simulation) -> Verilog Options, but this means adding one path for every "include" error the compiler detects, so it requires a lot of work. Moreover it doesn't seem to be always working, as it didn't fix the problem when I created a new project and the log content was the same as "vivado_include.log".
2) I created another project, this time copying and including all .sv, .svh, .v files from ips and rtl PULPissimo folders, so all files are in the same folder. I had to modify the `include directives of "fpnew" IP files in order to have correct `include paths. Moreover I had to comment out the "`ifdef synthesis" directive in hwpe_ctrl_interfaces.sv, as the compiler was not able to recognize "timeunit" and "timeprecision" keywords, although it should. Then, using xilinx related scripts inside "fpga/zcu102" folder as a guideline, I created the Xilinx IPs PULPissimo requires, that is two BRAMs and two clock generators, named xilinx_clk_mngr, xilinx_slow_clk_mngr, xilinx_private_ram and xilinx_interleaved_ram. Once I ran the behavioural simulation process, the compile phase went fine, but then the elaborate one was stopped with errors listed in "vivado_elaborate.log" file. I have to say I also read some warnings during compile phase, which details are again listed in "vivado_elaborate.log".
3) I created a new project, importing all files from ip and rtl folders. I've set some of the files referred by `include directives as "verilog header" from the files properties. Then I copied the registers.svh file inside "common_cells" folder of FPNEW ip, as the compiler was not able to find it. Moreover I had to comment out the "`ifdef synthesis" directive in hwpe_ctrl_interfaces.sv. However I still encountered errors after running behavioural simulation process, one of them referring to file riscv_alu.sv, with compiler indicating that "riscv_defines" packanot being declared.ge has not been declared. The log of this operation is inside "vivado_third_attempt.log".
All .log files are inside the attached "vivado_error_logs.zip" file.
Hope everything is clear. Thank you for your time!