[Vivado] behavioural simulation won't start

[andrea.spitale]

Hi Manuel,

thank you for your response. Ye, I didn't see there were scripts for the ZCU 102 board, my bad. So I used the provided makefile, but I get the following errors in vivado as soon as the process seems to finish:

Code:

ERROR: [Synth 8-1587] an enum variable may only be assigned to same enum typed variable or one of its values [/home/spitale/PULPissimo_git/ips/riscv/rtl/riscv_ex_stage.sv:445]
INFO: [Synth 8-2350] module riscv_ex_stage ignored due to previous errors [/home/spitale/PULPissimo_git/ips/riscv/rtl/riscv_ex_stage.sv:40]
Failed to read verilog '/home/spitale/PULPissimo_git/ips/riscv/rtl/riscv_ex_stage.sv'
2 Infos, 8 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details

any suggestion?