Failed at building the RTL simulation platform
#1
Hi, All:
I followed the instruction to setup a simple run environment, but always failed at the build stage, with following messages:

** Error: ../ips/pulp_soc/rtl/pulp_soc/soc_interconnect.sv(22): Cannot find `include file "axi/assign.svh" in directories:

    ../ips/pulp_soc/../../rtl/includes, ../ips/pulp_soc/rtl/include, ../ips/pulp_soc/../axi/axi/include, /eda/Mentor/Questa10.7/questasim/ovm-2.1.2/../verilog_src/ovm-2.1.2/src, /eda/Mentor/Questa10.7/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src

I checked all cloned files, found AXI, dm, ... etc, NOT downloaded. 

Could you someone help me on this issue?
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Failed at building the RTL simulation platform - by Jackie Zhang - 01-25-2021, 11:58 AM

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