Post Synthesis Simulation in ASIC
#1
Question 
Hi,
   I am trying to synthesize the pulpissimo, I don't find any documentation or specific script  for post-synthesis simulation but I have done the below steps

1) replaced the generic_memory, generic_rom with technology-related cells
2) synthesized soc_domain as top and have obtained synthesis netlist and its sdf file
3) I have replaced the soc_domain.sv with the synthesis netlist in sim/vcompile/rtl/pulpissimo.mk <-- all other files are same, not sure which files to keep and which one to remove 
3) I have added the CORE and CLK libs with -L option in sim/tcl_files/run.tcl

The modules gf2_fll , pulp_clock_gating , pulp_clock_mux2 , cluster_clock_gating , cluster_clock_inverter, pulp_clock_inverter are not synthesized, is any one these modules need to be synthesized for post-synthesis simulation?

what libraries should i need to keep in ./sim/tcl_files/config/vsim_ips.tcl ?

It will be great if someone can help me here

Vignajeth
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Messages In This Thread
Post Synthesis Simulation in ASIC - by vignajeth - 04-07-2021, 12:23 PM
RE: Post Synthesis Simulation in ASIC - by kgf - 04-07-2021, 12:34 PM

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