12-30-2021, 01:25 PM
Hi all,
I am planning to do some work on porting the Pulpissimo platform to several different FPGA boards. One will be Kintex KC705 and another one would Zynq ZC706. Potentially, there might also be a port to some of application specific boards, again, based on Kintex chip.
I have run an out-of-box run for Zedboard just to get the feeling about the sizes of different iPs. One thing that I've noticed is that the clock frequency is set to 20MHz for the Zedboard and that the Vivado synthesis/implementation does report a fail in timing closure even for such a low clock frequency.
My actual idea was to port to ZC706 and KC706 and to use a clock frequency of somewhere in the neighborhood of 80MHz-100MHz.
Is this something that should be achievable? What would be a maximal achievable frequency for FPGA synthesis?
In addition, have you been doing any synthesis runs for TSMC 40nm LP?
Thanks.
Cheers,
NK
I am planning to do some work on porting the Pulpissimo platform to several different FPGA boards. One will be Kintex KC705 and another one would Zynq ZC706. Potentially, there might also be a port to some of application specific boards, again, based on Kintex chip.
I have run an out-of-box run for Zedboard just to get the feeling about the sizes of different iPs. One thing that I've noticed is that the clock frequency is set to 20MHz for the Zedboard and that the Vivado synthesis/implementation does report a fail in timing closure even for such a low clock frequency.
My actual idea was to port to ZC706 and KC706 and to use a clock frequency of somewhere in the neighborhood of 80MHz-100MHz.
Is this something that should be achievable? What would be a maximal achievable frequency for FPGA synthesis?
In addition, have you been doing any synthesis runs for TSMC 40nm LP?
Thanks.
Cheers,
NK