12-19-2018, 01:31 PM
(This post was last modified: 12-19-2018, 01:32 PM by Mixermachine.)
Hello there,
I currently collect information for my bachelor thesis and want to compare popular RISC-V implementations.
You have a nice graphicÂ
Does there exist a documentation or has somebody knowledge about how the RISC-V cores match to for example ARM cores.
For example:
RI5CY <-> ARM cortex M0
or
PULPino <-> ARM cortex M0
Greetings from Munich,
Aaron
Edit:
The people over at Si-Five compare their cores here for example https://www.sifive.com/core-designer (scroll to the bottom)
I currently collect information for my bachelor thesis and want to compare popular RISC-V implementations.
You have a nice graphicÂ
Does there exist a documentation or has somebody knowledge about how the RISC-V cores match to for example ARM cores.
For example:
RI5CY <-> ARM cortex M0
or
PULPino <-> ARM cortex M0
Greetings from Munich,
Aaron
Edit:
The people over at Si-Five compare their cores here for example https://www.sifive.com/core-designer (scroll to the bottom)