Latest Pulpissimo RTL doesn't fit the nexysA7-100T FPGA

[AhmedZaky]

Hi, 

I have been trying to program Nexys A7 with the latest Pulpissimo RTL and I am encountering these issues, any clue? 

1. REPORT DETAILS
   

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UTLZ-1#1 Error
Resource utilization - PBlock:ROOT
RAMB18 and RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 288 of such cell types but only 270 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)ROOT
Related violations:
UTLZ-1#2 Error
Resource utilization - PBlock:ROOT
RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB36/FIFO cells than are available in the target device. This design requires 144 of such cell types but only 135 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)ROOT
Related violations:
UTLZ-1#3 Error
Resource utilization - PBlock:ROOT
RAMB36E1 over-utilized in Top Level Design (This design requires more RAMB36E1 cells than are available in the target device. This design requires 144 of such cell types but only 135 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)ROOT
Related violations:



Regards,