priviliged interrupts

[tswaehn]

I am using the machine and user mode on the pulp (CV32E40P). As far as I understand I need to set UTVEC and MTVEC to the corresponding locations of interrupt vector table. I also registered a handler for ex timer (machine mode handler + user mode handler individiually) and enabled the timer. Then I can enable the interrupts in MSTATUS or USTATUS. 

My observation is: 
* when beeing in user mode => interrupts are pushed to UTVEC and handled in user mode
* when beeing in machine mode => interrupts are pushed to MTVEC and handled in machine mode

However I was expecting some kind of configuration where all interrupts are preferably handled by machine mode (always) => where and how can I configure this? (I expected some implementation of medeleg and mideleg, but this doesnt seem to exist?)

any hints are welcome. thank you in advance.


***update***

if I leave the user interrupt in USTATUS disabled, then in both modes the handler of machine mode will be triggered. however as the user can enable the user interrupt in USTATUS, I would still expect the machine mode handler to be triggered with higher priority - thus should be triggered first => but that is not happening.

***hints***

An interrupt i will trap to M-mode (causing the privilege mode to change to M-mode) if all of the following are true: (a) either the current privilege mode is M and the MIE bit in the mstatus register is set, or the current privilege mode has less privilege than M-mode; (b) bit i is set in both mip and mie; and © if register mideleg exists, bit i is not set in mideleg.

reference