10-19-2024, 08:51 AM
I am trying to use the CV32E40P/RI5CY core in a school project and am having a lot of trouble with the setup. This is the first time using an open source core so forgive me if some questions seem silly.
I added all the RTLs according to the manifest here
https://github.com/openhwgroup/cv32e40p/...fest.flist
However, when I try to synthesize the module on Xilinx Vivado (2023.2), I do not have enough IO pins. Referring to a paper (https://ieeexplore.ieee.org/document/10420491), I noted that there are more BRAMs in their synthesis so I am trying to wrap the inputs and outputs of the core in BRAMs, which seems like the correct direction. The problem is that my synthesis will optimize away my core module. I don't quite know how the BRAM method works.
Could anyone share about how they went about wrapping their inputs into BRAMs. For example, do you use 3 separate BRAMs for the instruction memory, Data Memory, and a last BRAM for any outputs that come from the core module? Also, how do you read the instruction memory? I don't see any Program Counter module in the RI5CY code.
Thank you
I added all the RTLs according to the manifest here
https://github.com/openhwgroup/cv32e40p/...fest.flist
However, when I try to synthesize the module on Xilinx Vivado (2023.2), I do not have enough IO pins. Referring to a paper (https://ieeexplore.ieee.org/document/10420491), I noted that there are more BRAMs in their synthesis so I am trying to wrap the inputs and outputs of the core in BRAMs, which seems like the correct direction. The problem is that my synthesis will optimize away my core module. I don't quite know how the BRAM method works.
Could anyone share about how they went about wrapping their inputs into BRAMs. For example, do you use 3 separate BRAMs for the instruction memory, Data Memory, and a last BRAM for any outputs that come from the core module? Also, how do you read the instruction memory? I don't see any Program Counter module in the RI5CY code.
Thank you