10-25-2024, 07:13 PM
As far as I can understand you are trying to instantiate a RISC-V core on its own. While it is possible to construct a working system with memories and other peripherals, your life will be easier if you try an existing system where all these components have been instantiated.
From our group
https://github.com/pulp-platform/pulpissimo
https://github.com/pulp-platform/cheshire
are complete platforms that instantiate everything.
Although no FPGA mapping is yet available a simplified SoC we are now working on is Croc
https://github.com/pulp-platform/croc
And from our colleagues at EPFL there is the X-Heep
https://github.com/esl-epfl/x-heep
Check out also their FPGA emulation for X-HEEP
https://github.com/esl-epfl/x-heep-femu
From our group
https://github.com/pulp-platform/pulpissimo
https://github.com/pulp-platform/cheshire
are complete platforms that instantiate everything.
Although no FPGA mapping is yet available a simplified SoC we are now working on is Croc
https://github.com/pulp-platform/croc
And from our colleagues at EPFL there is the X-Heep
https://github.com/esl-epfl/x-heep
Check out also their FPGA emulation for X-HEEP
https://github.com/esl-epfl/x-heep-femu
Visit pulp-platform.org and follow us on twitter @pulp_platform