11-20-2019, 06:55 AM
Hi all,
First of all, thanks a lot for your help and support.
I was wondering if there is a synthesis - clean version of PULPissimo that's already released to the public. If not, is there any document / way to understand how the clock the distribution is going ?
What I understand, correct me if I am wrong, that in the case of:
1- FPGA, u r using a reference clock of 200 MHz to generate two internal clocks by divisions: A- Soc_clk = 20Mhz , B- periph_clk = 10Mhz.
2- In case of the RTL simulation, you r feeding from the TB a reference clock of ~ 32KHz and somehow, using DCO, FLL generating two clocks soc_clk = periph_clk = 17.5 MHz.
If I am correct, are this on-chip clock generation modules synthesizable? Or they should be mapped to IPs in the PDK ?
---------
Assuming that I want to drive the whole chip using the external clock, is it save to just remove all the " fll, DCO.. etc" modules and pass the signal through the modules to all the system components ? I mean the PAD_xtal_clk, pass it for the fc_subsystem, l2_memory .. etc and the system can work on that clock ? I already did simulation and it worked, but I am making sue that I didn't miss anything as I didn't test the system exhaustively.
Thanks in advance.
First of all, thanks a lot for your help and support.
I was wondering if there is a synthesis - clean version of PULPissimo that's already released to the public. If not, is there any document / way to understand how the clock the distribution is going ?
What I understand, correct me if I am wrong, that in the case of:
1- FPGA, u r using a reference clock of 200 MHz to generate two internal clocks by divisions: A- Soc_clk = 20Mhz , B- periph_clk = 10Mhz.
2- In case of the RTL simulation, you r feeding from the TB a reference clock of ~ 32KHz and somehow, using DCO, FLL generating two clocks soc_clk = periph_clk = 17.5 MHz.
If I am correct, are this on-chip clock generation modules synthesizable? Or they should be mapped to IPs in the PDK ?
---------
Assuming that I want to drive the whole chip using the external clock, is it save to just remove all the " fll, DCO.. etc" modules and pass the signal through the modules to all the system components ? I mean the PAD_xtal_clk, pass it for the fc_subsystem, l2_memory .. etc and the system can work on that clock ? I already did simulation and it worked, but I am making sue that I didn't miss anything as I didn't test the system exhaustively.
Thanks in advance.