Synthesis failed on ZedBoard (riscv_ex_stage.sv)

[akurth]

Hi,

Thanks for reporting this.

If this is the line where the error occurs, it could be that the declaration and definition of C_DIV, i.e., 

Code:

localparam C_DIV = FP_DIVSQRT ? fpnew_pkg::MERGED : fpnew_pkg::DISABLED;

misses a type.  The type should be fpnew_pkg::unit_type_t.  Could you try if replacing that line with

Code:

localparam fpnew_pkg::unit_type_t C_DIV = FP_DIVSQRT ? fpnew_pkg::MERGED : fpnew_pkg::DISABLED;

solves the problem?

(According to the SystemVerilog standard, C_DIV in the code above should implicitly get that type, because "A parameter declaration with no type or range specification shall default to the type and range of the final value assigned to the parameter, [...]" (Section 6.20.2 in IEEE 1800-2012).  But that is probably too complex for Vivado to implement.)