QuestaSim Installation for RTL Simulation
(07-28-2022, 05:26 AM)kgf Wrote: Hello,

Questasim is a commercial EDA tool from Siemens/Mentor. It comes with an installation tool and plenty of documentation as well as support. If you are in academia, there are academic programs your institution can take advantage of to get access to it. As a company you will have to acquire a license (and pay). Unfortunately if you are an unaffiliated individual there are fewer options. 

Technically PULP does not require a specific simulator (i.e. Questasim), but we know our code runs when we use this simulator. Other commercial simulators (VCS, ncsim/xcellium, aldec etc..) should in theory all work.. There are also open source RTL simulators like verilator. 

The practical reality is that there are still some SystemVerilog constructs that one or the other simulator does not support (or has difficulties) which can cause issues (verilator for example does not support assertions) with the code as it is written. None of it is a serious problem, given some time the code can be cleaned up (or simplified), newer versions of the tools have better support reducing these issues, at the very worst, simulator specific IFDEFs can be added. BUT, we state that we use Questasim, so that people are aware with which simulator we usually work (we also ended up using both VCS and xcellium in different projects) meaning that we cleaned it up to make sure it will work with Questasim.  

We are moving more and more to have code that supports Verilator, but again, the code base is large, and there are could still be some bits and pieces that needs to be cleaned up for Verilator. As this is an open source project, this is also where contributions are needed, we are happy to accept PR for fixes for compatibility issues of simulators. 

Hope that helps

Thank you for your timely response. It appears that I do not have access to QuestaSim, but we do have Xcelium. As such, I tried to build the RTL simulation platform for Pulpissimo, which is said to have Xcelium support on its github page. However, when I tried to run make, I am still running into an abundance of errors that seem to suggest that it is still trying to run QuestaSim commands through the usage of vsim. The errors are as follows:

make checkout
find: 'work': No such file or directory
./bender checkout
touch Bender.lock
make scripts
find: 'work': No such file or directory
make[1]: Entering directory `/home_local/[LOCALE]/pulpissimo'
echo 'set ROOT [file normalize [file dirname [info script]]/..]' > sim/compile.tcl
./bender script vsim \
       --vlog-arg="-suppress 2583 -suppress 13314 \"+incdir+\$ROOT/rtl/includes\"" --vcom-arg="" \
       -t rtl -t test \
       | grep -v "set ROOT" >> sim/compile.tcl
mkdir -p fpga/pulpissimo/tcl/generated
./bender script vivado -t fpga -t xilinx > fpga/pulpissimo/tcl/generated/compile.tcl
make[1]: Leaving directory `/home_local/[LOCALE]/pulpissimo'
make build
find: 'work': No such file or directory
cd sim && make all
make[1]: Entering directory `/home_local/[LOCALE]/pulpissimo/sim'
make -C ../rtl/tb/remote_bitbang all
make[2]: Entering directory `/home_local/[LOCALE]/pulpissimo/rtl/tb/remote_bitbang'
cc -MT remote_bitbang.o -MMD -MP -MF ./.d/remote_bitbang.Td -std=gnu11 -fno-strict-aliasing -Wall -Wextra -Wno-missing-field-initializers -Wno-unused-function -Wno-missing-braces -O2 -g -march=native -DENABLE_LOGGING -DNDEBUG -fPIC -I./  \
       -c  remote_bitbang.c -o remote_bitbang.o
ld -shared -E --exclude-libs ALL -o  \
       remote_bitbang.o sim_jtag.o
make[2]: Leaving directory `/home_local/[LOCALE]/pulpissimo/rtl/tb/remote_bitbang'
vsim -c -do 'source compile.tcl; quit'
make[1]: vsim: Command not found
make[1]: *** [build] Error 127
make[1]: Leaving directory `/home_local/[LOCALE]/pulpissimo/sim'
make: *** [build] Error 2

Is there some sort of variable or path that I'm supposed to be setting in order for it to run with Xcelium? How should I proceed in this case?

Thank you in advance.

Messages In This Thread
RE: QuestaSim Installation for RTL Simulation - by achen9 - 08-01-2022, 02:45 AM

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