11-22-2022, 11:17 AM
Hello,
I would like to deploy the pulp-platform in an Artix fpga but I don't know what files to include in the design and simulation, as well.
Are there any tree file which explains how the files are connected on RTL and Simulation level so that know which is the top level ?
I would like to deploy the pulp-platform in an Artix fpga but I don't know what files to include in the design and simulation, as well.
Are there any tree file which explains how the files are connected on RTL and Simulation level so that know which is the top level ?