Synthesis 8 core pulp for ASIC
#1
Hello !

I want to synthesis the pulp SoC for 65 nm ASIC technology. Given that I have the Synopsys Compiler available is there a guide as to how proper synthesis of the pulp (with 8 RI5CY) cores can be carried out on the such that the hierarchy of the system is properly maintained during optimizations. 

Is there some example script available to direct the Synopsys compiler (or some other compiler) to perform proper synthesis. 
The final goal is to be able to perform power measurements on the synthesised design. Also, is this power analysis possible with the given repository of the pulp project on github?
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Messages In This Thread
Synthesis 8 core pulp for ASIC - by Athena - 02-11-2019, 04:41 PM
RE: Synthesis 8 core pulp for ASIC - by kgf - 02-11-2019, 05:11 PM
RE: Synthesis 8 core pulp for ASIC - by kgf - 02-28-2019, 07:08 AM

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