Synthesis 8 core pulp for ASIC
#4
Yes, it is possible to generate a netlist (of PULP based systems) using Design Compiler. All ASICs we have made were done this way.

We do not have sample Design Compiler scripts, as this requires technology dependent customizations. What design compiler does is take your HDL description and map it to a set of cells from a target library so that the decsrioption takes physical form. There are some cells (clock gates, I/O cells, memory macros) that need to be specific to the technology. In addition the constraints that you have (clock speed, input output delays etc), need to be adjusted to the technology as well.

I am afraid for this, you will need to have some technical help, it can not be done in a technology agnostic way.

But in principle (ignoring all the technical little details), just analyze everything. elaborate the top file and run compile_ultra, and it will work. There is nothing out of the ordinary needed to get PULP to compile on Design Compiler

I hope that helps
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Messages In This Thread
Synthesis 8 core pulp for ASIC - by Athena - 02-11-2019, 04:41 PM
RE: Synthesis 8 core pulp for ASIC - by kgf - 02-11-2019, 05:11 PM
RE: Synthesis 8 core pulp for ASIC - by kgf - 02-28-2019, 07:08 AM

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