05-07-2019, 04:19 PM
Hi,
are you having some scripts or tools to help making correct code parsing for synthesis?
I have made my own list, but don't know which files should be included. For example there is axi_slice_dc_master_wrap.sv under axi and pulp_soc.
Is there some automation hidden for src_files.yml files under IPs and RTL?
Currently when running synthesis with dc_shell, it gives errors from some of IPs. I assume that those are not needed in Pulpino implementation.
are you having some scripts or tools to help making correct code parsing for synthesis?
I have made my own list, but don't know which files should be included. For example there is axi_slice_dc_master_wrap.sv under axi and pulp_soc.
Is there some automation hidden for src_files.yml files under IPs and RTL?
Currently when running synthesis with dc_shell, it gives errors from some of IPs. I assume that those are not needed in Pulpino implementation.