Pulpissimo L2 memory access via JTAG

[pschiavo]

Hello,

I am trying to write and read L2 memory via JTAG . According to datasheet memory map it should be in 0x1c000000...0x1c080000. and in soc_bus_defines there is definition
// MASTER PORT TO L2
`define SOC_L2_START_ADDR        32'h1C00_0000
`define SOC_L2_END_ADDR          32'h1FFF_FFFF


However the above parameters are not used anywhere and I can not succesfully write and read to that area. I get always zeros from  any memory address that i have tried.
So where is the memory located actually ? 
I went through the related RTL codes and found local parameter TCDM_START_ADDRESS, which is set to diffrent memory area, and it looked that might be the used area but still the memory access is not working.

As background:
I have succesfylly read and written quite a many peripheral resister, SOC control registers etc, so the JTAG link as such works.
I have implemented Pulpissomo on KIntex FPGA on Genesys board. The xilinx memories seem to be in shape.

Regards, skor

Hello skor,


to read/write L2 memory with the JTAG please refer to these memory ranges between line 260 and 264

https://github.com/pulp-platform/pulp_so...ct.sv#L260

As far as I can tell, you should be able to R/W from 1c00_0000 so it is strange that you see all 0s.

The L2 memory is organized as 3 banks, of which one is interleaved.

The 3 banks have the following ranges:

Bank0: [1C00_0000, 1C00_8000)
Bank1: [1C00_8000, 1C01_0000)
Bank Interleaved: [1C01_0000, 1C08_2000)

you may want to try to read and write to the same bank to see whether it works. I can tell that in all our implementations on Silicon this has always worked so far

Best
Davide