Cheshire with two cores

[andlo47]

Hi all,

I'm trying to generate a bit file for Cheshire v0.1.0 with two cores for the Genesys2 board using Vivado 2023.2, but get an error stating that timing constraints are not met.
I can generate the bit file from an earlier commit, f316617, of the Cheshire repo. I did remove the USB support as it would not fit on the FPGA of Genesys2.

I'm quite new to this and would appreciate any help. I'm not sure where to start looking.

Regards,
/Andreas

[kgf]

I am guessing that some of the additions proved a bit too much for the timing constraints. You could (in most cases) relax the constraints to get through it. Note that for most PULP IP, the code is not FPGA optimized, we use FPGAs for emulation and not as the primary target. That is why, the speed at which it works is not much of an issue. Our usual targets are ASIC designs where the optimizations may differ quite a bit from FPGAs (due to internal resources like BRAMs, DSPs etc).

Of course it is not like the timing contraints should go from 50ns to 5000ns.. that could point out to an issue somewhere