What do I need to do before a taping out of PULPino?

[zhouqiang]

Hello，
I am a student  a complete novice in SOC design. Our tutor wants to implement a RISCV chip design on the extra area of the MPW. If I want to tape out PULPino, what should I verify first?

As far as I know, PULPino is a very mature project, and it has been taped out in different processes, so my current idea is:

1. Perform a Verilog simulation test. The assembly code of the instruction is compiled into a binary file to be read by Verilog's readmemh function, and then all instructions are tested one by one until all instructions pass the test. This part of the test should only involve the operation of the instruction set in the RISCY core.

2. Perform FPGA prototype verification on PULPino SOC. The purpose of this process is to download the SOC's Verilog code to the FPGA and then run the program on the FPGA. It may be necessary to use GDB and OpenOCD for debugging.

Is my idea correct? Does the PULPino project support the above two verifications? Can you give me some advice? And what should be noted in the tool chain, environment, SDK, etc.?

Thanks
zhouqiang

[kgf]

Hello Zhouqiang,

There is nothing really wrong with your general description, and the methods you describe are not wrong. However, there are some other issues you need to look at as well.

• RI5CY is the core, and PULPIno is the system that adda memories and peripherals around it.
  
• Just making a PULPino is usually not very interesting for most people we discuss with. The usual use case, is that people take the core (RI5CY) and build it as part of their own system. They then use PULPino as a development/verification system.
  
• The description you have in 1) would be needed for such a customized system (Take RI5CY merge with your own custom system). For PULPino, complete testbenches for System Verilog exist. So if you are not changing anything and using it as it is, you can directly go ahead.
  
• Initializing the memories with readmem is a common way of accelerating simulation, however, if you want to have (later) a chip working, you also have to make sure that you can program the system externally (either through a JTAG interface, external SPI or smtg else).  
  
• There is already an FPGA prototype available for the Zed board. You can directly use it. That particular solution uses a more custom debugging solution, but generally what you want in 2) already exists you can use it directly.
  
• If you want to make an ASIC with any of the PULP items, there is still some work to be done. We can not release technology specific information (clock generators, I/O cells, memories), so there is a generic library that emulates the behavior of these cells. Once you select a technology (say TSMC65), you need to replace these generic cells with technology specific cells. Especially memories will have a large impact on the overall performance of the system, and you might need to adjust your constraints around what is feasible in the technology.
  
• We try to keep the code tool chain neutral, I think it should work with any combination of major EDA tools as well as increasing support for open source EDA.
  

Wish you all the luck in your project.

[zhouqiang]

Hello Zhouqiang,

There is nothing really wrong with your general description, and the methods you describe are not wrong. However, there are some other issues you need to look at as well.

• RI5CY is the core, and PULPIno is the system that adda memories and peripherals around it.
  
• Just making a PULPino is usually not very interesting for most people we discuss with. The usual use case, is that people take the core (RI5CY) and build it as part of their own system. They then use PULPino as a development/verification system.
  
• The description you have in 1) would be needed for such a customized system (Take RI5CY merge with your own custom system). For PULPino, complete testbenches for System Verilog exist. So if you are not changing anything and using it as it is, you can directly go ahead.
  
• Initializing the memories with readmem is a common way of accelerating simulation, however, if you want to have (later) a chip working, you also have to make sure that you can program the system externally (either through a JTAG interface, external SPI or smtg else).  
  
• There is already an FPGA prototype available for the Zed board. You can directly use it. That particular solution uses a more custom debugging solution, but generally what you want in 2) already exists you can use it directly.
  
• If you want to make an ASIC with any of the PULP items, there is still some work to be done. We can not release technology specific information (clock generators, I/O cells, memories), so there is a generic library that emulates the behavior of these cells. Once you select a technology (say TSMC65), you need to replace these generic cells with technology specific cells. Especially memories will have a large impact on the overall performance of the system, and you might need to adjust your constraints around what is feasible in the technology.
  
• We try to keep the code tool chain neutral, I think it should work with any combination of major EDA tools as well as increasing support for open source EDA.
  

Wish you all the luck in your project.

Hello kgf，
Thank you for your detailed answer. How should I get started with the toolchain, SDK and environment? Have they all been assembled in PULPino (https://github.com/pulp-platform/pulpino)? I tried to follow the steps of the readme in PULPino, but I even got it wrong in the first step, (./update-ips.py). Is it because the environment of the entire project is not set up? How should I build the entire project environment step by step?

[kgf]

at the moment there is still no open source environment that would allow you to make an ASIC tape-out. You will need to have these tools installed in your system. This is unfortunately not trivial, and I suggest you talk to the person that is in charge of maintaining the EDA tools in your group/company.

The readme should actually be correct step by step instructions (at least to the best of my knowledge). If something is not working, there usually is an error message, and if we are lucky, it could give us some clues as where to look next. It would not be fair that we keep intentionally wrong information on GitHub.

In addition if you find anything missing or not clear, you can actually issue a pull request (for the README.md) as well.

[zhouqiang]

at the moment there is still no open source environment that would allow you to make an ASIC tape-out. You will need to have these tools installed in your system. This is unfortunately not trivial, and I suggest you talk to the person that is in charge of maintaining the EDA tools in your group/company.

The readme should actually be correct step by step instructions (at least to the best of my knowledge). If something is not working, there usually is an error message, and if we are lucky, it could give us some clues as where to look next. It would not be fair that we keep intentionally wrong information on GitHub.

In addition if you find anything missing or not clear, you can actually issue a pull request (for the README.md) as well.

hello gf，
Thank you for your prompt reply. I think you may have misunderstood what I mean. In my system I have installed the EDA tools (DC, ICC, PT, calibre, etc.) needed for ASIC design. What I want to know is the riscv toolchain, SDK and ISA required for PULPino debugging. Are they integrated in the PULPino system（https://github.com/pulp-platform/pulpino）? Or how can I build these environments step by step? Is there a detailed manual telling me what to do?

[kgf]

The instructions should be there already https://github.com/pulp-platform/pulpino. As it is an earlier release it uses a cmake flow.