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hello，
When doing DC synthesis for the PULPino system, I tried to generate a 512B boot ROM using the contents of boot_code.sv, but I found that the data size in boot_code.sv is 548×32, which is obviously not 512B. How can I solve this problem?
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Hello,
I am not sure I understand. Just generate a ROM that is large enough for the Boot code.. Why does it have to be 512 Bytes?
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Posts: 27
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(05-07-2019, 10:08 AM)kgf Wrote: Hello,
I am not sure I understand. Just generate a ROM that is large enough for the Boot code.. Why does it have to be 512 Bytes?
Hello kgf，
The size of the boot rom is 512B in the memory map (figure2.1) in the datasheet, and its address is 0x0008 0000-0x0008 0200, so I want to generate a ROM with a size of 512B. I generated the ROM according to boot_code.sv, but the size of the data in boot_code.sv is 548×32, which is my doubt. Is my understanding correct? Should I generate ROM based on boot_code.sv?
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Ahh I see now.. I think there is an older figure.. The ROM can grow starting from 0x0008 0000.. There is nothing in the map until 0x0010 0000.. I think an older version indeed just had 512 Bytes, but it can be larger, there is nothing that stops it..
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(05-07-2019, 02:15 PM)kgf Wrote: Ahh I see now.. I think there is an older figure.. The ROM can grow starting from 0x0008 0000.. There is nothing in the map until 0x0010 0000.. I think an older version indeed just had 512 Bytes, but it can be larger, there is nothing that stops it..
The size of boot_code.sv is 548×32，so we have to generate a rom whose size is 1024×32，almos 4KB，a little too big，especially compared with 512B.
Posts: 27
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(05-07-2019, 02:15 PM)kgf Wrote: Ahh I see now.. I think there is an older figure.. The ROM can grow starting from 0x0008 0000.. There is nothing in the map until 0x0010 0000.. I think an older version indeed just had 512 Bytes, but it can be larger, there is nothing that stops it..
hello，
Now I want to verify the correctness of the generated boot rom. I want to determine if this ROM works, so I replaced the boot_code.sv in the original RTL folder with the Verilog file of the ROM's function model. Then, I recompile the RTL code: "make vcompile", execute "make helloworld.vsim", can I verify the correctness of the generated ROM in this way?
