PULPissimo Synthesis and Clock Distribution

[AhmedZaky]

Hi all, 

First of all, thanks a lot for your help and support.

I was wondering if there is a synthesis - clean version of PULPissimo that's already released to the public. If not, is there any document / way to understand how the clock the distribution is going ? 

What I understand, correct me if I am wrong, that in the case of: 

1- FPGA, u r using a reference clock of 200 MHz to generate two internal clocks by divisions: A- Soc_clk = 20Mhz , B- periph_clk = 10Mhz.

2- In case of the RTL simulation, you r feeding from the TB a reference clock of ~ 32KHz and somehow, using DCO, FLL generating two clocks soc_clk = periph_clk = 17.5 MHz. 

If I am correct, are this on-chip clock generation modules synthesizable? Or they should be mapped to IPs in the PDK ? 

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Assuming that I want to drive the whole chip using the external clock, is it save to just remove all the " fll, DCO.. etc" modules and pass the signal through the modules to all the system components ? I mean the PAD_xtal_clk, pass it for the fc_subsystem, l2_memory .. etc and the system can work on that clock ? I already did simulation and it worked, but I am making sue that I didn't miss anything as I didn't test the system exhaustively. 

Thanks in advance.

[kgf]

Hello,

First of all, we do not have a 'better' internal PULPissimo system internally, the GitHUb release is the one we are also using for our projects.  What happens is that once we have an ASIC project, then we have an internal version that has a process specific instantiation (i.e. for GF22FDX) which contains memory cuts, I/O pads, clock gating cells etc that are specific to that technology. Until now, we do not have a way to release these technology specific components (NDAs we have signed do not allow us to release them). But the RTL code base is still the same, and any issues we find, fixes we make are contributed to the main branch.

Generally we do not optimize our code for FPGA targets. In your questions
1) Refers to one implementation we use for the FPGA board (there is a clock on the board that is available)
2) Is the one that usually ends up how we use it in an ASIC. We use a slow XTAL oscillator externally (32kHz) and have our own (technology mapped) FLL that can be programmed to generate the clocks we need inside. (Similarly we can also not release the FLL openly.. yet..)

I have to check the code, but I'm pretty sure even in the 32kHz ASIC/FLL configuration we add a bypass mux so that the reference clock goes into the system directly. 

You can change and adapt the clocking according to your needs, the domains are clearly separated and should be easily manageable. What you describe should work fine. We know of people that have done some simple optimizations so that the code maps 'better' to a given FPGA target. Note that, it could get tedious to update the optimized code whenever the generic code gets a fix or improvement. 

I hope this helps