Resource Utilization of PULPino/PULPissimo in FPGA

[Mwind]

Hello,

I am currently evaluating the use of RISC-V processors in FPGAs. Has anyone implemented a PULPino or PULPissimo on an FPGA and can you make rough statements about the resource usage?

I would appreciate any information. Thanks in advance.

[kgf]

There are already some pre-prepared scripts to get it to run on FPGAs see for example for PULPissimo
 https://github.com/pulp-platform/pulpiss...aster/fpga

[zorrolee777]

Hello,

I am currently evaluating the use of RISC-V processors in FPGAs. Has anyone implemented a PULPino or PULPissimo on an FPGA and can you make rough statements about the resource usage?

I would appreciate any information. Thanks in advance.

Hello Mwind,

How's your project going? I'm also looking for some information about the resource utilization of the PULPissimo in different FPGAs. As we need to put some Add-ons on it, I'm wondering how many resources would be left if the PULPissimo was implemented on different FPGAs? Thanks in advance.

Zongru

[LarsKeuninckx]

Hello,

I am currently evaluating the use of RISC-V processors in FPGAs. Has anyone implemented a PULPino or PULPissimo on an FPGA and can you make rough statements about the resource usage?

I would appreciate any information. Thanks in advance.

Hello Mwind,

How's your project going? I'm also looking for some information about the resource utilization of the PULPissimo in different FPGAs. As we need to put some Add-ons on it, I'm wondering how many resources would be left if the PULPissimo was implemented on different FPGAs? Thanks in advance.

Zongru

Hi,
after creating the bitstream file .bit for a certain board target, check this file:
pulpissimo/fpga/pulpissimo-<yourboard>/pulpissimo-<yourboard>.runs/impl_1/xilinx_pulpissimo_utilization_placed.rpt.


Here is an exert from mine, for a Xilinx Artix 7a100tcsg324-1 :
 

Code:

+----------------------------+-------+-------+-----------+-------+
|          Site Type         |  Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs                 | 36209 |     0 |     63400 | 57.11 |
|   LUT as Logic             | 36197 |     0 |     63400 | 57.09 |
|   LUT as Memory            |    12 |     0 |     19000 |  0.06 |
|     LUT as Distributed RAM |     0 |     0 |           |       |
|     LUT as Shift Register  |    12 |     0 |           |       |
| Slice Registers            | 20930 |     0 |    126800 | 16.51 |
|   Register as Flip Flop    | 20905 |     0 |    126800 | 16.49 |
|   Register as Latch        |    25 |     0 |    126800 |  0.02 |
| F7 Muxes                   |  1340 |     0 |     31700 |  4.23 |
| F8 Muxes                   |   225 |     0 |     15850 |  1.42 |
+----------------------------+-------+-------+-----------+-------+

Cheers!

[zorrolee777]

Hello,

I am currently evaluating the use of RISC-V processors in FPGAs. Has anyone implemented a PULPino or PULPissimo on an FPGA and can you make rough statements about the resource usage?

I would appreciate any information. Thanks in advance.

Hello Mwind,

How's your project going? I'm also looking for some information about the resource utilization of the PULPissimo in different FPGAs. As we need to put some Add-ons on it, I'm wondering how many resources would be left if the PULPissimo was implemented on different FPGAs? Thanks in advance.

Zongru

Hi,
after creating the bitstream file .bit for a certain board target, check this file:
pulpissimo/fpga/pulpissimo-<yourboard>/pulpissimo-<yourboard>.runs/impl_1/xilinx_pulpissimo_utilization_placed.rpt.


Here is an exert from mine, for a Xilinx Artix 7a100tcsg324-1 :
 

Code:

+----------------------------+-------+-------+-----------+-------+
|          Site Type         |  Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs                 | 36209 |     0 |     63400 | 57.11 |
|   LUT as Logic             | 36197 |     0 |     63400 | 57.09 |
|   LUT as Memory            |    12 |     0 |     19000 |  0.06 |
|     LUT as Distributed RAM |     0 |     0 |           |       |
|     LUT as Shift Register  |    12 |     0 |           |       |
| Slice Registers            | 20930 |     0 |    126800 | 16.51 |
|   Register as Flip Flop    | 20905 |     0 |    126800 | 16.49 |
|   Register as Latch        |    25 |     0 |    126800 |  0.02 |
| F7 Muxes                   |  1340 |     0 |     31700 |  4.23 |
| F8 Muxes                   |   225 |     0 |     15850 |  1.42 |
+----------------------------+-------+-------+-----------+-------+

Cheers!

Thanks!