Latest Pulpissimo RTL doesn't fit the nexysA7-100T FPGA

[AhmedZaky]

Hi, 

I have been trying to program Nexys A7 with the latest Pulpissimo RTL and I am encountering these issues, any clue? 

1. REPORT DETAILS
   

---

UTLZ-1#1 Error
Resource utilization - PBlock:ROOT
RAMB18 and RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 288 of such cell types but only 270 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)ROOT
Related violations:
UTLZ-1#2 Error
Resource utilization - PBlock:ROOT
RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB36/FIFO cells than are available in the target device. This design requires 144 of such cell types but only 135 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)ROOT
Related violations:
UTLZ-1#3 Error
Resource utilization - PBlock:ROOT
RAMB36E1 over-utilized in Top Level Design (This design requires more RAMB36E1 cells than are available in the target device. This design requires 144 of such cell types but only 135 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)ROOT
Related violations:



Regards,

[kgf]

Seems like the memory is too large to fit.. It should not be too difficult to reduce the memory instantiated.

Cheers

[AhmedZaky]

Hi KGF,

I was able to fit the latest PULPISSIMO to Nexys-A7. However, I have a question:

Previously, when I used to gynesys2, I was able to connect 2 USB cables, one for the UART and one for the JTAG, and this is how I was able to connect to the RISC-V using the debugger.

For Nexys7, there is only 1 USB port, which I believe would be used for the UART interface. As for the JTAG, I will need to use the PMOD A, am I right in my understanding? If yes, what's the best possible way to connect the PC to the PMOD as I haven't used the PMOD interface before? I can't seem to find a cable/board that converts PMOD to JTAG USB.

Much appreciated!

[kgf]

oops good one..

I am not so experienced with these bards. I assume that the PMOD boards are connected directly to the GPIO pins of the FPGA. For example this could maybe work:
https://digilent.com/shop/pmod-usbuart-u...interface/
Not sure though. I do not think anyone here tried to run PULPissimo on Nexsys. Technically speaking there would be a JTAG connector somewhere on the board, so instead of simulating JTAG through USB, you could use a USB to JTAG dongle and connect.. But I am just writing these from the top of my head, not because I have tried, or know that these work. So please take this with a grain of salt..