xilinx memories in pulpissimo L2
#1
Hi,

In Pulpissimo in l2_ram_multi_bank.sv there is hooks for xilinx memories:
`ifdef PULP_FPGA_EMUL

      logic [NB_BANKS-1:0][7:0]   wea;

      genvar                      i,j;
      generate
         for(i=0; i<NB_BANKS; i++)
         begin : CUTS
            for(j=0; j<8; j++)
            assign wea[i][j] = ~mem_slave[i].csn & ~mem_slave[i].wen & mem_slave[i].be[j];

            xilinx_l2_mem_8192x64 l2_mem_i (
               .clka  ( clk_i                                ),
               .rsta  ( ~rst_ni                              ),
               .ena   ( ~mem_slave[i].csn                    ),
               .wea   ( wea[i]                               ),
               .addra ( mem_slave[i].add[MEM_ADDR_WIDTH-1:0] ),
               .dina  ( mem_slave[i].wdata                   ),
               .douta ( mem_slave[i].rdata                   )
            );
         end
      endgenerate

Have you tested this is working?

Regards, skor
Reply
#2
(06-10-2019, 06:47 AM)skor Wrote: Hi,

In Pulpissimo in l2_ram_multi_bank.sv there is hooks for xilinx memories:
`ifdef PULP_FPGA_EMUL

      logic [NB_BANKS-1:0][7:0]   wea;

      genvar                      i,j;
      generate
         for(i=0; i<NB_BANKS; i++)
         begin : CUTS
            for(j=0; j<8; j++)
            assign wea[i][j] = ~mem_slave[i].csn & ~mem_slave[i].wen & mem_slave[i].be[j];

            xilinx_l2_mem_8192x64 l2_mem_i (
               .clka  ( clk_i                                ),
               .rsta  ( ~rst_ni                              ),
               .ena   ( ~mem_slave[i].csn                    ),
               .wea   ( wea[i]                               ),
               .addra ( mem_slave[i].add[MEM_ADDR_WIDTH-1:0] ),
               .dina  ( mem_slave[i].wdata                   ),
               .douta ( mem_slave[i].rdata                   )
            );
         end
      endgenerate

Have you tested this is working?

Regards, skor

Hi skor,

Indeed, this code is not working anymore. If you have a look at the fpga branch of PULPissimo on Github you will find that this code segment and a couple of similar ones have been replaced with generic wrappers (e.g. in this case called fpga_interleaved_ram) that are intended to instantiate FPGA specific implementations. 

The FPGA port of PULPissimo on this branch is almost ready to be released (bitstream generation should already work out of the box for the Genesys2 board) and will be merged to master and publicly announced in the next couple of days.

If you have the same board available you can already try it out with:

Code:
 
git checkout fpga
./update-ips
cd fpga
make genesys2

Porting the code to a different board should be quite straigth-forward. You can start with a copy of the pulpissimo-genesys2 directory and modify the file fpga-settings.mk, constraints/genesys2.xdc, tcl/run.tcl and, if necessary, the implementations of the generic wrappers. To load, debug and execute programs on PULPissimo you most likely will also have to modify the configuration file for OpenOCD (openocd-genesys2.cfg) corresponding to the way you expose the JTAG interface on your board. 

To seamlessly integrate support for a new board into the existing flow you can also modify the Makefile in the fpga subdirectory. 
Pull-Requests are welcome  Wink
Reply


Forum Jump: