Pulpissimo bitstream generation.
#1
Hello,

I got the following errors during bitstream generation for genesys2 board.

Code:
open_run: Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 7121.617 ; gain = 0.000 ; free physical = 3356 ; free virtual = 8201
# exec mkdir -p reports/
# exec rm -rf reports/*
# check_timing                                                              -file reports/${project}.check_timing.rpt
# report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack   -file reports/${project}.timing_WORST_100.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
INFO: [Timing 38-78] ReportTimingParams: -max_paths 100 -nworst 100 -delay_type max -sort_by slack.
# report_timing -nworst 1 -delay_type max -sort_by group                    -file reports/${project}.timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by group.
# report_utilization -hierarchical                                          -file reports/${project}.utilization.rpt
INFO: [Common 17-206] Exiting Vivado at Thu Jun 27 15:20:28 2019...
make[1]: Leaving directory `********/pulpissimo/fpga/pulpissimo-genesys2'
cp pulpissimo-genesys2/pulpissimo.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_genesys2.bit
cp: cannot stat ‘pulpissimo-genesys2/pulpissimo.runs/impl_1/xilinx_pulpissimo.bit’: No such file or directory
make: *** [genesys2] Error 1

Even the console shows error, the .bit file is generated. I loaded the .bit file to genesys2 board and try to read and write in the memory with the plpbridge. Which didn't work.

Code:
$ plpbridge --chip=pulpissimo --cable=ftdi@digilent write --addr=0x1c000000 --size=32 --value=0x12345678
Found ftdi device i:0x403:0x6010:0
Connecting to ftdi device i:0x403:0x6010:0
$ plpbridge --chip=pulpissimo --cable=ftdi@digilent read --addr=0x1c000000 --size=32
Found ftdi device i:0x403:0x6010:0
Connecting to ftdi device i:0x403:0x6010:0
ft2232: did not get a start bit from the AXI module in 1s
1c000000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1c000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00



I also tried to communicate with RISC-V debug module with openOCD. Got the following output.

Code:
Open On-Chip Debugger 0.10.0+dev-00619-g91faf1a (2019-06-27-13:52)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
adapter speed: 1000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
  TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
0 riscv.unknown0         Y     0x00000000 0x10102001     5 0x01  0x03
1 riscv.cpu              Y     0x00000000 0x249511c3     5 0x01  0x03
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.unknown0 tap/device found: 0x10102001 (mfg: 0x000 (<invalid>), part: 0x0102, ver: 0x1)
Info : JTAG tap: riscv.cpu tap/device found: 0x249511c3 (mfg: 0x0e1 (Wintec Industries), part: 0x4951, ver: 0x2)
Info : datacount=2 progbufsize=8
Info : Examined RISC-V core; found 32 harts
Info :  hart 0: currently disabled
Info :  hart 1: currently disabled
Info :  hart 2: currently disabled
Info :  hart 3: currently disabled
Info :  hart 4: currently disabled
Info :  hart 5: currently disabled
Info :  hart 6: currently disabled
Info :  hart 7: currently disabled
Info :  hart 8: currently disabled
Info :  hart 9: currently disabled
Info :  hart 10: currently disabled
Info :  hart 11: currently disabled
Info :  hart 12: currently disabled
Info :  hart 13: currently disabled
Info :  hart 14: currently disabled
Info :  hart 15: currently disabled
Info :  hart 16: currently disabled
Info :  hart 17: currently disabled
Info :  hart 18: currently disabled
Info :  hart 19: currently disabled
Info :  hart 20: currently disabled
Info :  hart 21: currently disabled
Info :  hart 22: currently disabled
Info :  hart 23: currently disabled
Info :  hart 24: currently disabled
Info :  hart 25: currently disabled
Info :  hart 26: currently disabled
Info :  hart 27: currently disabled
Info :  hart 28: currently disabled
Info :  hart 29: currently disabled
Info :  hart 30: currently disabled
Info :  hart 31: currently disabled
openocd: src/target/riscv/riscv.c:2522: riscv_set_current_hartid: Assertion `riscv_hart_enabled(target, hartid)' failed.
Aborted (core dumped)
Could you please point out what am i missing here ?
Regards,
naprpo
Reply
#2
I have the same issue. Tried both riscv-openocd from riscv repo and from PULP repo.
I also have another question: how can I connect external AXI module to Pulpissimo?
Reply
#3
(06-27-2019, 12:43 PM)naprpo Wrote:
Hello,

I got the following errors during bitstream generation for genesys2 board.

Code:
open_run: Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 7121.617 ; gain = 0.000 ; free physical = 3356 ; free virtual = 8201
# exec mkdir -p reports/
# exec rm -rf reports/*
# check_timing                                                              -file reports/${project}.check_timing.rpt
# report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack   -file reports/${project}.timing_WORST_100.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
INFO: [Timing 38-78] ReportTimingParams: -max_paths 100 -nworst 100 -delay_type max -sort_by slack.
# report_timing -nworst 1 -delay_type max -sort_by group                    -file reports/${project}.timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by group.
# report_utilization -hierarchical                                          -file reports/${project}.utilization.rpt
INFO: [Common 17-206] Exiting Vivado at Thu Jun 27 15:20:28 2019...
make[1]: Leaving directory `********/pulpissimo/fpga/pulpissimo-genesys2'
cp pulpissimo-genesys2/pulpissimo.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_genesys2.bit
cp: cannot stat ‘pulpissimo-genesys2/pulpissimo.runs/impl_1/xilinx_pulpissimo.bit’: No such file or directory
make: *** [genesys2] Error 1

Even the console shows error, the .bit file is generated. I loaded the .bit file to genesys2 board and try to read and write in the memory with the plpbridge. Which didn't work.

Code:
$ plpbridge --chip=pulpissimo --cable=ftdi@digilent write --addr=0x1c000000 --size=32 --value=0x12345678
Found ftdi device i:0x403:0x6010:0
Connecting to ftdi device i:0x403:0x6010:0
$ plpbridge --chip=pulpissimo --cable=ftdi@digilent read --addr=0x1c000000 --size=32
Found ftdi device i:0x403:0x6010:0
Connecting to ftdi device i:0x403:0x6010:0
ft2232: did not get a start bit from the AXI module in 1s
1c000000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1c000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00



I also tried to communicate with RISC-V debug module with openOCD. Got the following output.

Code:
Open On-Chip Debugger 0.10.0+dev-00619-g91faf1a (2019-06-27-13:52)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
adapter speed: 1000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
  TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
0 riscv.unknown0         Y     0x00000000 0x10102001     5 0x01  0x03
1 riscv.cpu              Y     0x00000000 0x249511c3     5 0x01  0x03
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.unknown0 tap/device found: 0x10102001 (mfg: 0x000 (<invalid>), part: 0x0102, ver: 0x1)
Info : JTAG tap: riscv.cpu tap/device found: 0x249511c3 (mfg: 0x0e1 (Wintec Industries), part: 0x4951, ver: 0x2)
Info : datacount=2 progbufsize=8
Info : Examined RISC-V core; found 32 harts
Info :  hart 0: currently disabled
Info :  hart 1: currently disabled
Info :  hart 2: currently disabled
Info :  hart 3: currently disabled
Info :  hart 4: currently disabled
Info :  hart 5: currently disabled
Info :  hart 6: currently disabled
Info :  hart 7: currently disabled
Info :  hart 8: currently disabled
Info :  hart 9: currently disabled
Info :  hart 10: currently disabled
Info :  hart 11: currently disabled
Info :  hart 12: currently disabled
Info :  hart 13: currently disabled
Info :  hart 14: currently disabled
Info :  hart 15: currently disabled
Info :  hart 16: currently disabled
Info :  hart 17: currently disabled
Info :  hart 18: currently disabled
Info :  hart 19: currently disabled
Info :  hart 20: currently disabled
Info :  hart 21: currently disabled
Info :  hart 22: currently disabled
Info :  hart 23: currently disabled
Info :  hart 24: currently disabled
Info :  hart 25: currently disabled
Info :  hart 26: currently disabled
Info :  hart 27: currently disabled
Info :  hart 28: currently disabled
Info :  hart 29: currently disabled
Info :  hart 30: currently disabled
Info :  hart 31: currently disabled
openocd: src/target/riscv/riscv.c:2522: riscv_set_current_hartid: Assertion `riscv_hart_enabled(target, hartid)' failed.
Aborted (core dumped)
Could you please point out what am i missing here ?
Regards,
naprpo
Hi naprpo,

Please excuse the late response but I was away on holidays.

The error you got during the bitstream generation seems to be only related to the final copy command that would copy the generated bitstream file to the top directory. It seems like those files were created at a different location in your case, therefore, the cp command fails which is not an issue regarding functionality. Regarding the plpbridge that connects to the old debug module: I never tested the old debug module but only used the new riscv-debug module with openocd so I cannot really comment on that part.

Could you tell me the patch where you found the generated bitstream and bin file?

The problem you have with the riscv-debug module and openocd is related to a long outstanding issue regarding non-contiguous hartids.

For now, you need to use the patched version of riscv-openocd in the PULP-SDK to workaround the problem. The patched openocd should be installed with newer versions of the PULP-SDK (i successfully tried with commit id 06c5dc6) under pkg/openocd.
Reply
#4
(07-11-2019, 02:28 PM)meggiman Wrote:
(06-27-2019, 12:43 PM)naprpo Wrote:
Hello,

I got the following errors during bitstream generation for genesys2 board.

Code:
open_run: Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 7121.617 ; gain = 0.000 ; free physical = 3356 ; free virtual = 8201
# exec mkdir -p reports/
# exec rm -rf reports/*
# check_timing                                                              -file reports/${project}.check_timing.rpt
# report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack   -file reports/${project}.timing_WORST_100.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
INFO: [Timing 38-78] ReportTimingParams: -max_paths 100 -nworst 100 -delay_type max -sort_by slack.
# report_timing -nworst 1 -delay_type max -sort_by group                    -file reports/${project}.timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by group.
# report_utilization -hierarchical                                          -file reports/${project}.utilization.rpt
INFO: [Common 17-206] Exiting Vivado at Thu Jun 27 15:20:28 2019...
make[1]: Leaving directory `********/pulpissimo/fpga/pulpissimo-genesys2'
cp pulpissimo-genesys2/pulpissimo.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_genesys2.bit
cp: cannot stat ‘pulpissimo-genesys2/pulpissimo.runs/impl_1/xilinx_pulpissimo.bit’: No such file or directory
make: *** [genesys2] Error 1

Even the console shows error, the .bit file is generated. I loaded the .bit file to genesys2 board and try to read and write in the memory with the plpbridge. Which didn't work.

Code:
$ plpbridge --chip=pulpissimo --cable=ftdi@digilent write --addr=0x1c000000 --size=32 --value=0x12345678
Found ftdi device i:0x403:0x6010:0
Connecting to ftdi device i:0x403:0x6010:0
$ plpbridge --chip=pulpissimo --cable=ftdi@digilent read --addr=0x1c000000 --size=32
Found ftdi device i:0x403:0x6010:0
Connecting to ftdi device i:0x403:0x6010:0
ft2232: did not get a start bit from the AXI module in 1s
1c000000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1c000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00



I also tried to communicate with RISC-V debug module with openOCD. Got the following output.

Code:
Open On-Chip Debugger 0.10.0+dev-00619-g91faf1a (2019-06-27-13:52)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
adapter speed: 1000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
  TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
0 riscv.unknown0         Y     0x00000000 0x10102001     5 0x01  0x03
1 riscv.cpu              Y     0x00000000 0x249511c3     5 0x01  0x03
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.unknown0 tap/device found: 0x10102001 (mfg: 0x000 (<invalid>), part: 0x0102, ver: 0x1)
Info : JTAG tap: riscv.cpu tap/device found: 0x249511c3 (mfg: 0x0e1 (Wintec Industries), part: 0x4951, ver: 0x2)
Info : datacount=2 progbufsize=8
Info : Examined RISC-V core; found 32 harts
Info :  hart 0: currently disabled
Info :  hart 1: currently disabled
Info :  hart 2: currently disabled
Info :  hart 3: currently disabled
Info :  hart 4: currently disabled
Info :  hart 5: currently disabled
Info :  hart 6: currently disabled
Info :  hart 7: currently disabled
Info :  hart 8: currently disabled
Info :  hart 9: currently disabled
Info :  hart 10: currently disabled
Info :  hart 11: currently disabled
Info :  hart 12: currently disabled
Info :  hart 13: currently disabled
Info :  hart 14: currently disabled
Info :  hart 15: currently disabled
Info :  hart 16: currently disabled
Info :  hart 17: currently disabled
Info :  hart 18: currently disabled
Info :  hart 19: currently disabled
Info :  hart 20: currently disabled
Info :  hart 21: currently disabled
Info :  hart 22: currently disabled
Info :  hart 23: currently disabled
Info :  hart 24: currently disabled
Info :  hart 25: currently disabled
Info :  hart 26: currently disabled
Info :  hart 27: currently disabled
Info :  hart 28: currently disabled
Info :  hart 29: currently disabled
Info :  hart 30: currently disabled
Info :  hart 31: currently disabled
openocd: src/target/riscv/riscv.c:2522: riscv_set_current_hartid: Assertion `riscv_hart_enabled(target, hartid)' failed.
Aborted (core dumped)
Could you please point out what am i missing here ?
Regards,
naprpo
Hi naprpo,

Please excuse the late response but I was away on holidays.

The error you got during the bitstream generation seems to be only related to the final copy command that would copy the generated bitstream file to the top directory. It seems like those files were created at a different location in your case, therefore, the cp command fails which is not an issue regarding functionality. Regarding the plpbridge that connects to the old debug module: I never tested the old debug module but only used the new riscv-debug module with openocd so I cannot really comment on that part.

Could you tell me the patch where you found the generated bitstream and bin file?

The problem you have with the riscv-debug module and openocd is related to a long outstanding issue regarding non-contiguous hartids.

For now, you need to use the patched version of riscv-openocd in the PULP-SDK to workaround the problem. The patched openocd should be installed with newer versions of the PULP-SDK (i successfully tried with commit id 06c5dc6) under pkg/openocd.

Hi meggiman,

Thanks for the replay. I hope you enjoyed your holiday.

The .bin and .bit file are generated in 'pulpissimo/fpga/pulpissimo-genesys2/pulpissimo_genesys2.runs/impl_1' path. It is different path then given in the Makefile.

I am able to successfully lunch the patched openocd and connect with gdb. But still have some issues. I am able to load the binary file. Also able to set the breakpoint. After running the app, it never reachs the breakpoint. Forever continuing...
Here is how it looks, i am trying to run 'hello' example.
Code:
$ riscv32-unknown-elf-gdb build/pulpissimo/test/test
GNU gdb (GDB) 7.12.50.20170505-git
Copyright (C) 2016 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.  Type "show copying"
and "show warranty" for details.
This GDB was configured as "--host=x86_64-pc-linux-gnu --target=riscv32-unknown-elf".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from build/pulpissimo/test/test...done.
(gdb) target remote localhost:3333
Remote debugging using localhost:3333
warning: Target-supplied registers are not supported by the current architecture
0x1a000080 in ?? ()
(gdb) load
Loading section .data_tiny_fc, size 0x328 lma 0x1c000004
Loading section .init_array, size 0x24 lma 0x1c00032c
Loading section .fini_array, size 0xc lma 0x1c000350
Loading section .rodata, size 0x16c lma 0x1c00035c
Loading section .data, size 0x1e4 lma 0x1c000cd0
Loading section .vectors, size 0xa0 lma 0x1c008000
Loading section .text, size 0x20b8 lma 0x1c0080a0
Loading section .l2_data, size 0x10 lma 0x1c00a158
Start address 0x1c008080, load size 10256
Transfer rate: 18 KB/sec, 1282 bytes/write.
(gdb) disas main
Dump of assembler code for function main:
   0x1c0083be <+0>:    addi    sp,sp,-32
   0x1c0083c0 <+2>:    sw    s0,24(sp)
   0x1c0083c2 <+4>:    lui    s0,0xf4
   0x1c0083c6 <+8>:    sw    s1,20(sp)
   0x1c0083c8 <+10>:    sw    ra,28(sp)
   0x1c0083ca <+12>:    lui    s1,0x1c000
   0x1c0083ce <+16>:    addi    s0,s0,575 # 0xf423f
   0x1c0083d2 <+20>:    addi    a0,s1,860 # 0x1c00035c
   0x1c0083d6 <+24>:    jal    ra,0x1c009606 <printf>
   0x1c0083da <+28>:    sw    zero,12(sp)
   0x1c0083dc <+30>:    lw    a5,12(sp)
   0x1c0083de <+32>:    blt    s0,a5,0x1c0083d2 <main+20>
   0x1c0083e2 <+36>:    lw    a5,12(sp)
   0x1c0083e4 <+38>:    addi    a5,a5,1
   0x1c0083e6 <+40>:    sw    a5,12(sp)
   0x1c0083e8 <+42>:    lw    a5,12(sp)
   0x1c0083ea <+44>:    ble    a5,s0,0x1c0083e2 <main+36>
   0x1c0083ee <+48>:    j    0x1c0083d2 <main+20>
End of assembler dump.
(gdb) list
11     * distributed under the License is distributed on an "AS IS" BASIS,
12     * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13     * See the License for the specific language governing permissions and
14     * limitations under the License.
15     */
16    
17    #include <stdio.h>
18    
19    unsigned int __rt_iodev_uart_baudrate = 115200;
20    
(gdb)
21    int main()
22    {
23      while (1) {
24        printf("Hello World!\n\r");
25        for (volatile int i=0; i<1000000; i++);
26       }
27      return 0;
28    }
(gdb) b 24
Breakpoint 1 at 0x1c0083d2: file test.c, line 24.
(gdb) c
Continuing.

And this is how it looks in openocd

Code:
adapter speed: 1000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
  TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
0 riscv.unknown0         Y     0x00000000 0x10102001     5 0x01  0x03
1 riscv.cpu              Y     0x00000000 0x249511c3     5 0x01  0x03
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.unknown0 tap/device found: 0x10102001 (mfg: 0x000 (<invalid>), part: 0x0102, ver: 0x1)
Info : JTAG tap: riscv.cpu tap/device found: 0x249511c3 (mfg: 0x0e1 (Wintec Industries), part: 0x4951, ver: 0x2)
Info : datacount=2 progbufsize=8
Info : Examined RISC-V core; found 1024 harts
Info :  hart 0: currently disabled
Info :  hart 1: currently disabled
.
.
.
Info :  hart 991: currently disabled
Info :  hart 992: XLEN=32, misa=0x0
.
.
.
Info :  hart 1021: currently disabled
Info :  hart 1022: currently disabled
Info :  hart 1023: currently disabled
Info : Listening on port 3333 for gdb connections
Ready for Remote Connections
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : accepting 'gdb' connection on tcp/3333

if is stop the process with ctrl-c i get the following respose:


Code:
^Cunable to halt hart 992
 dmcontrol=0x83e00001
 dmstatus =0x00030c82
Remote failure reply: E0E
(gdb)

Now i am using the Pulp-sdk (commit id:  3256fe7) and Pulpissimo newest version from the fpga branch.

Br, Narayan
Reply
#5
Hi naprpo,

First of all, there is another detail I forgot to mention in the README (I will revise it and try to document it better for future users):
You need to tell the SDK which frequency PULPissimo is running with so the SDK can configure the right value for the UART's clock divider. Otherwise the baudrate will be wrong.
In order to do so define the following global variables in you source code:

int __rt_fpga_fc_frequency = 40000000;
int __rt_fpga_periph_frequency = 20000000;

If you didn't change anything in the bitstream generation script these two lines should configure the SDK to use the frequencies of 40MHz for the Core and 20MHz for the SoC that are used by default during Synthesis.

However, since you don't see any output at all (even with the wrong frequency breakpoints should work), there is probably another issue with your binary. ( I just successfully tried it with commit id 3256fe7, BTW: I suppose you didn't forget to run make on the SDK after checkout and sourced again configs/pulpissimo.sh and configs/fpgas/pulpissimo/genesys2.sh before recompilation of the SDK and the binary?). Could you send me the source code, the disassembly (run 'make dis>test.S') and the compiled elf binary so I can try it myself?
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#6
Hey,

I am stuck also at that error " openocd: src/target/riscv/riscv.c:2530: riscv_set_current_hartid: Assertion `riscv_hart_enabled(target, hartid)' failed. ", I've read the comments but I couldn't locate that patched openocd that comes with the SDK. May you please elaborate more one this ?

Thanks !
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#7
(07-15-2019, 08:28 AM)AhmedZaky Wrote: Hey,

I am stuck also at that error " openocd: src/target/riscv/riscv.c:2530: riscv_set_current_hartid: Assertion `riscv_hart_enabled(target, hartid)' failed. ", I've read the comments but I couldn't locate that patched openocd that comes with the SDK. May you please elaborate more one this  ?

Thanks !

Hi AhmedZaky,

Did you check the folder pulp-sdk/scripts?

I found the info there.

Regards,
naprpo
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#8
(07-15-2019, 08:14 AM)meggiman Wrote: Hi naprpo,

First of all, there is another detail I forgot to mention in the README (I will revise it and try to document it better for future users):
You need to tell the SDK which frequency PULPissimo is running with so the SDK can configure the right value for the UART's clock divider. Otherwise the baudrate will be wrong.
In order to do so define the following global variables in you source code:

int __rt_fpga_fc_frequency = 40000000;
int __rt_fpga_periph_frequency = 20000000;

If you didn't change anything in the bitstream generation script these two lines should configure the SDK to use the frequencies of 40MHz for the Core and 20MHz for the SoC that are used by default during Synthesis.

However, since you don't see any output at all (even with the wrong frequency breakpoints should work), there is probably another issue with your binary. ( I just successfully tried it with commit id 3256fe7, BTW: I suppose you didn't forget to run make on the SDK after checkout and sourced again configs/pulpissimo.sh and configs/fpgas/pulpissimo/genesys2.sh before recompilation of the SDK and the binary?). Could you send me the source code, the disassembly (run 'make dis>test.S') and the compiled elf binary so I can try it myself?

Hi meggiman,

Thanks for the help. I had the issues with SDK buid.
It is working now.

Regards,
naprpo
Reply
#9
(07-15-2019, 08:28 AM)AhmedZaky Wrote: Hey,

I am stuck also at that error " openocd: src/target/riscv/riscv.c:2530: riscv_set_current_hartid: Assertion `riscv_hart_enabled(target, hartid)' failed. ", I've read the comments but I couldn't locate that patched openocd that comes with the SDK. May you please elaborate more one this  ?

Thanks !

Hi AhmedZaky,

I just realized that the patched Openocd is not installed by default if you do not have access to the artifactory server (file server at ETH that contains precompiled binaries). However 
I revised the README in the fpga branch and added some sections on how to install the patched OpenOCD from source. Please follow the instructions at https://github.com/pulp-platform/pulpiss...nd-openocd.
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#10
Hi meggi,

Thank you very much on your help with OpenOCD. By the way, do you have any idea how to integrate 3rd party module into PULPissimo via AXI interface? I have tried connect it to AXI interface in the top level of pulp_soc (which is used for cluster) and soc_interconnect but both of them don't work.

Thank you in advance.
Dao
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