Pulpissimo bitstream generation.

[naprpo]

Hello,

I got the following errors during bitstream generation for genesys2 board.

Code:

open_run: Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 7121.617 ; gain = 0.000 ; free physical = 3356 ; free virtual = 8201
# exec mkdir -p reports/
# exec rm -rf reports/*
# check_timing                                                              -file reports/${project}.check_timing.rpt
# report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack   -file reports/${project}.timing_WORST_100.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
INFO: [Timing 38-78] ReportTimingParams: -max_paths 100 -nworst 100 -delay_type max -sort_by slack.
# report_timing -nworst 1 -delay_type max -sort_by group                    -file reports/${project}.timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by group.
# report_utilization -hierarchical                                          -file reports/${project}.utilization.rpt
INFO: [Common 17-206] Exiting Vivado at Thu Jun 27 15:20:28 2019...
make[1]: Leaving directory `********/pulpissimo/fpga/pulpissimo-genesys2'
cp pulpissimo-genesys2/pulpissimo.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_genesys2.bit
cp: cannot stat ‘pulpissimo-genesys2/pulpissimo.runs/impl_1/xilinx_pulpissimo.bit’: No such file or directory
make: *** [genesys2] Error 1

Even the console shows error, the .bit file is generated. I loaded the .bit file to genesys2 board and try to read and write in the memory with the plpbridge. Which didn't work.

Code:

$ plpbridge --chip=pulpissimo --cable=ftdi@digilent write --addr=0x1c000000 --size=32 --value=0x12345678
Found ftdi device i:0x403:0x6010:0
Connecting to ftdi device i:0x403:0x6010:0
$ plpbridge --chip=pulpissimo --cable=ftdi@digilent read --addr=0x1c000000 --size=32
Found ftdi device i:0x403:0x6010:0
Connecting to ftdi device i:0x403:0x6010:0
ft2232: did not get a start bit from the AXI module in 1s
1c000000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1c000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I also tried to communicate with RISC-V debug module with openOCD. Got the following output.

Code:

Open On-Chip Debugger 0.10.0+dev-00619-g91faf1a (2019-06-27-13:52)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
adapter speed: 1000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
  TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
0 riscv.unknown0         Y     0x00000000 0x10102001     5 0x01  0x03
1 riscv.cpu              Y     0x00000000 0x249511c3     5 0x01  0x03
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.unknown0 tap/device found: 0x10102001 (mfg: 0x000 (<invalid>), part: 0x0102, ver: 0x1)
Info : JTAG tap: riscv.cpu tap/device found: 0x249511c3 (mfg: 0x0e1 (Wintec Industries), part: 0x4951, ver: 0x2)
Info : datacount=2 progbufsize=8
Info : Examined RISC-V core; found 32 harts
Info :  hart 0: currently disabled
Info :  hart 1: currently disabled
Info :  hart 2: currently disabled
Info :  hart 3: currently disabled
Info :  hart 4: currently disabled
Info :  hart 5: currently disabled
Info :  hart 6: currently disabled
Info :  hart 7: currently disabled
Info :  hart 8: currently disabled
Info :  hart 9: currently disabled
Info :  hart 10: currently disabled
Info :  hart 11: currently disabled
Info :  hart 12: currently disabled
Info :  hart 13: currently disabled
Info :  hart 14: currently disabled
Info :  hart 15: currently disabled
Info :  hart 16: currently disabled
Info :  hart 17: currently disabled
Info :  hart 18: currently disabled
Info :  hart 19: currently disabled
Info :  hart 20: currently disabled
Info :  hart 21: currently disabled
Info :  hart 22: currently disabled
Info :  hart 23: currently disabled
Info :  hart 24: currently disabled
Info :  hart 25: currently disabled
Info :  hart 26: currently disabled
Info :  hart 27: currently disabled
Info :  hart 28: currently disabled
Info :  hart 29: currently disabled
Info :  hart 30: currently disabled
Info :  hart 31: currently disabled
openocd: src/target/riscv/riscv.c:2522: riscv_set_current_hartid: Assertion `riscv_hart_enabled(target, hartid)' failed.
Aborted (core dumped)

Could you please point out what am i missing here ?
Regards,
naprpo