Pulpissimo bitstream generation.
#8
(07-15-2019, 08:14 AM)meggiman Wrote: Hi naprpo,

First of all, there is another detail I forgot to mention in the README (I will revise it and try to document it better for future users):
You need to tell the SDK which frequency PULPissimo is running with so the SDK can configure the right value for the UART's clock divider. Otherwise the baudrate will be wrong.
In order to do so define the following global variables in you source code:

int __rt_fpga_fc_frequency = 40000000;
int __rt_fpga_periph_frequency = 20000000;

If you didn't change anything in the bitstream generation script these two lines should configure the SDK to use the frequencies of 40MHz for the Core and 20MHz for the SoC that are used by default during Synthesis.

However, since you don't see any output at all (even with the wrong frequency breakpoints should work), there is probably another issue with your binary. ( I just successfully tried it with commit id 3256fe7, BTW: I suppose you didn't forget to run make on the SDK after checkout and sourced again configs/pulpissimo.sh and configs/fpgas/pulpissimo/genesys2.sh before recompilation of the SDK and the binary?). Could you send me the source code, the disassembly (run 'make dis>test.S') and the compiled elf binary so I can try it myself?

Hi meggiman,

Thanks for the help. I had the issues with SDK buid.
It is working now.

Regards,
naprpo
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Messages In This Thread
Pulpissimo bitstream generation. - by naprpo - 06-27-2019, 12:43 PM
RE: Pulpissimo bitstream generation. - by gideros - 07-01-2019, 07:36 AM
RE: Pulpissimo bitstream generation. - by naprpo - 07-12-2019, 12:20 PM
RE: Pulpissimo bitstream generation. - by naprpo - 07-15-2019, 11:02 AM
RE: Pulpissimo bitstream generation. - by naprpo - 07-15-2019, 08:59 AM
RE: Pulpissimo bitstream generation. - by gideros - 07-16-2019, 02:22 AM

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