Buid failed

[hithaishi_t]

Hello,

I am trying to build RTL simulation platform for pulpissimo and for the command "make clean lib build opts", I am getting the following error.

Modifying /root/altera/16.0/modelsim_
ase/linuxaloem/../modelsim.ini
Building L2_tcdm_hybrid_interco/soc_interconnect
Building adv_dbg_if/adv_dbg_if
Building apb2per/apb2per
Building apb_adv_timer/apb_adv_timer
Building apb_fll_if/apb_fll_if
Building apb_gpio/apb_gpio
Building apb_node/apb_node
Building apb_interrupt_cntrl/apb_interrupt_cntrl
Building axi_node/axi_node
Building axi_slice/axi_slice
Building axi_slice_dc/axi_slice_dc
Building axi_mem_if/axi_mem_if
Building timer_unit/timer_unit
Building common_cells/common_cells_all
** Error: ../ips/common_cells/src/id_queue.sv(268): Questa has encountered an unexpected internal error: ../../src/vlog/vgentd.c(515). Please contact Questa support at http://supportnet.mentor.com/
/root/pulp-sdk/pulpissimo/sim/vcompile//ips/common_cells.mk:73: recipe for target '/root/pulp-sdk/pulpissimo/sim/modelsim_libs/common_cells_lib/common_cells_all.vmake' failed
make[2]: *** [/root/pulp-sdk/pulpissimo/sim/modelsim_libs/common_cells_lib/common_cells_all.vmake] Error 2
/root/pulp-sdk/pulpissimo/sim//vcompile/ips.mk:14: recipe for target 'build' failed
make[1]: *** [build] Error 2
Makefile:33: recipe for target 'build' failed
make: *** [build] Error 2

Can you please tell me how to rectify this?

Thanks and Regards
Hithaishi

[kgf]

It seems like you are using the Altera version of Questasim. This is a simulator that is packaged with Altera, to be used for developing Altera FPGA designs. In the past people have commented that this version is not usable for PULP projects. It is not necessarily a mistake on the PULP source code, it is more that, the Altera Edition seems to be a limited version of the whole simulator.

It should work with a 'regular' Mentor Questasim

[hithaishi_t]

It seems like you are using the Altera version of Questasim. This is a simulator that is packaged with Altera, to be used for developing Altera FPGA designs. In the past people have commented that this version is not usable for PULP projects. It is not necessarily a mistake on the PULP source code, it is more that, the Altera Edition seems to be a limited version of the whole simulator.

It should work with a 'regular' Mentor Questasim

Hi....
I have installed altera modelsim 10.4d not the questasim. I'm so confused and couldn't understand why am I getting the error for questasim

Regards
Hithaishi

[kgf]

Sorry if it was not clear:
We have heard that it does NOT work on Altera Modelsim editions. Our scripts/Makefiles will work with a proper Mentor Questasim installation (at least thatis what we have and test them).

If someone has the time to understand and fix issues related to Altera Modelsim (or any other) simulator we will be very happy to add the support as well.

[KMTesfai]

Sorry if it was not clear:
We have heard that it does NOT work on Altera Modelsim editions. Our scripts/Makefiles will work with a proper Mentor Questasim installation (at least thatis what we have and test them).

If someone has the time to understand and fix issues related to Altera Modelsim (or any other) simulator we will be very happy to add the support as well.

Hello @kgf,

I got the same error message too, is there any solution proposed yet for the build to support ModelSim - INTEL FPGA STARTER EDITION 2021.1

[kgf]

Hello,

I see online many people that have managed to get this running for PULP on the Altera/Intel edition. The idea of open source is that the community also 'contributes'. Please open an issue on GitHub, and/or if you manage to find a solution please make a pull request so that this issue can be resolved.

At ETH Zurich and University of Bologna, we do not have the time/resources to understand why the compilation process does not go through for tools we do not even access to, so unless someone from the community contributes a solution, or at least explains what they did, we will not be able to solve it.

Note that the Altera/Intel Modelsim edition is NOT the proper questasim, but a limited version that Altera/Intel delivers together with its FPGA boards. They have obtained a license to redistribute it and that apparently comes with some restrictions and level of support. Most probably some statements are not recognized/supported or they exceed some set limits. Both of which could probably easily solved..