10-22-2019, 01:03 PM
Hello,
I am currently trying to implement a HWPE into the PULPissimo platform.
Now i am facing a few problems and it would be great if someone could help me clarify some things.
This might be a rather long thread with quite a few questions but i hope that this will not only help me but also other people that (might) face the same or similar problems as i do.
What i am trying to do to understand the interaction between the L2 Memory, the TCDM interconnect and a HWPE, is to make my own simple HWPE.
At first it should only consist of a couple of registers and be able to read/write from/to the L2 Memory.
This means that data flow is the thing i am interested in at the moment.
If this simple HWPE works and can successfully read/write then a more complex HWPE can easily follow.
So first i was reading the HWPE Interface Specifications and the Systemverilog code to get a rough overview of the (possible) interactions between L2 Memory <-> TCDM <-> HWPE.
This is how i think things are working so please correct me if i am wrong:
There are (at least) two components that can do read/write operations on the L2 Memory.
First the core which has an instruction memory interface and a data memory interface.
The fc_subsystem has two XBAR_TCDM_BUS.Master ports used by the core.
One for data (l2_data_master) and one for instructions (l2_instr_master).
These connect the core with the XBAR_TCDM_BUS.Slave ports of the soc_interconnect_wrap.
The soc_interconnect itself then has a RISC data port and a RISC instruction port.
Now this is where things start to get more confusing to me.
But the important thing is that the core can use its data memory interface to interact with the L2 Memory.
This means i know that it is possible to send signals to the L2 Memory (req, addr, etc.) for read/write operations.
So one possibility would be to have the HWPE interact with the L2 Memory the same way the core does.
This brings up some question:
1) Can the core and the HWPE share the same bus? If yes, would that mean that the core would have to stall if the HWPE is using the bus?
2) If they don't share the same bus and you create a new connection to the L2 Memory based on the cores data memory interface, how could you handle possible errors regarding Write-After-Read, etc. I am not sure if the request/response trees are able to handle such scenarios as PULPissimo is a single core system. Then again there are also multi-core variants but i haven't read anything about data flow in such PULP systems.
3) Similar to 2) but this time the HWPE would use more than one port (similar to how the current HWPE implementation works).
The second component that can do read/write operations on the L2 Memory is the HWPE.
At least in the pulp-rt-example the data is loaded into the L2 Memory.
Now the HWPE uses streams and i tried to make my own HWPE use only one master port.
Questions regarding the HWPE variant:
1) Can you use a single port for read/write or do you need at least two (source+sink)?
2) I tried the pulp-rt-example for the accelerator and reduced the number of master ports down to two. This failed as it seems just changing the parameters for the number of master ports is not enough. You probably have to do some changes in the stream controller, right? (maybe even more changes)
So in a nutshell: I am trying to implement my own HWPE in a PULPissimo platform. Currently the HWPE should only be able to read/write from/to the L2 Memory. At first i wanted to use only one port for that. If that works i wanted to increase the number of ports.
The questions are:
- Does it make sense to use the same port as the core?
- Does it make sense to create a new port which mimics the port of the core?
- Would the best/easiest/most efficient way be to just use the ports of the HWPE which are already defined and just replace the example HWPE with my own?
- What are the limits of the number of ports for both the core style variant as well as the HWPE variant?
If anything is unclear please feel free to ask and i will try my best to give further details.
Thank you very much.
LPLA
I am currently trying to implement a HWPE into the PULPissimo platform.
Now i am facing a few problems and it would be great if someone could help me clarify some things.
This might be a rather long thread with quite a few questions but i hope that this will not only help me but also other people that (might) face the same or similar problems as i do.
What i am trying to do to understand the interaction between the L2 Memory, the TCDM interconnect and a HWPE, is to make my own simple HWPE.
At first it should only consist of a couple of registers and be able to read/write from/to the L2 Memory.
This means that data flow is the thing i am interested in at the moment.
If this simple HWPE works and can successfully read/write then a more complex HWPE can easily follow.
So first i was reading the HWPE Interface Specifications and the Systemverilog code to get a rough overview of the (possible) interactions between L2 Memory <-> TCDM <-> HWPE.
This is how i think things are working so please correct me if i am wrong:
There are (at least) two components that can do read/write operations on the L2 Memory.
First the core which has an instruction memory interface and a data memory interface.
The fc_subsystem has two XBAR_TCDM_BUS.Master ports used by the core.
One for data (l2_data_master) and one for instructions (l2_instr_master).
These connect the core with the XBAR_TCDM_BUS.Slave ports of the soc_interconnect_wrap.
The soc_interconnect itself then has a RISC data port and a RISC instruction port.
Now this is where things start to get more confusing to me.
But the important thing is that the core can use its data memory interface to interact with the L2 Memory.
This means i know that it is possible to send signals to the L2 Memory (req, addr, etc.) for read/write operations.
So one possibility would be to have the HWPE interact with the L2 Memory the same way the core does.
This brings up some question:
1) Can the core and the HWPE share the same bus? If yes, would that mean that the core would have to stall if the HWPE is using the bus?
2) If they don't share the same bus and you create a new connection to the L2 Memory based on the cores data memory interface, how could you handle possible errors regarding Write-After-Read, etc. I am not sure if the request/response trees are able to handle such scenarios as PULPissimo is a single core system. Then again there are also multi-core variants but i haven't read anything about data flow in such PULP systems.
3) Similar to 2) but this time the HWPE would use more than one port (similar to how the current HWPE implementation works).
The second component that can do read/write operations on the L2 Memory is the HWPE.
At least in the pulp-rt-example the data is loaded into the L2 Memory.
Now the HWPE uses streams and i tried to make my own HWPE use only one master port.
Questions regarding the HWPE variant:
1) Can you use a single port for read/write or do you need at least two (source+sink)?
2) I tried the pulp-rt-example for the accelerator and reduced the number of master ports down to two. This failed as it seems just changing the parameters for the number of master ports is not enough. You probably have to do some changes in the stream controller, right? (maybe even more changes)
So in a nutshell: I am trying to implement my own HWPE in a PULPissimo platform. Currently the HWPE should only be able to read/write from/to the L2 Memory. At first i wanted to use only one port for that. If that works i wanted to increase the number of ports.
The questions are:
- Does it make sense to use the same port as the core?
- Does it make sense to create a new port which mimics the port of the core?
- Would the best/easiest/most efficient way be to just use the ports of the HWPE which are already defined and just replace the example HWPE with my own?
- What are the limits of the number of ports for both the core style variant as well as the HWPE variant?
If anything is unclear please feel free to ask and i will try my best to give further details.
Thank you very much.
LPLA