Understanding the TCDM interconnect and implementing HWPEs
#4
Hi LPLA, some more detail with respect to the second part of your question.

Quote:Questions regarding the HWPE variant:
1) Can you use a single port for read/write or do you need at least two (source+sink)?

Well, both things! You can use a single port but you need two different streamers to manage incoming streams (source, to generate loads) and outgoing ones (sink, to generate stores). The separate "streams" of loads and stores generated by source and sink can be then mixed by means of a dynamic mux or a static mux. In the former case, the mux is essentially a level of interconnect arbitrating between conflicting accesses. In the latter, it is really a multiplexer - there is a static signal selecting which "stream" of loads and stores is selected.

Quote:2) I tried the pulp-rt-example for the accelerator and reduced the number of master ports down to two. This failed as it seems just changing the parameters for the number of master ports is not enough. You probably have to do some changes in the stream controller, right? (maybe even more changes)

In general, what is in this repo https://github.com/pulp-platform/hwpe-mac-engine is provided as an example, assume you have to change it. In the case of the toy MAC engine, there are three source and one sink modules, what you probably need is only two.

Quote:- Does it make sense to use the same port as the core? 

If by this you mean the same physical memory, yes -- but you'll need a layer of arbitration in between. Also, I do not recommend doing it.


Quote:- Does it make sense to create a new port which mimics the port of the core?

This is essentially how it already works, except that HWPE ports jump a few demux/interconnection layers as they are not capable of accessing some parts of L2 (non-interleaved memory).

Quote:- Would the best/easiest/most efficient way be to just use the ports of the HWPE which are already defined and just replace the example HWPE with my own?

By far the simplest and most recommended route. You can simply tie the unused master ports so that their req, add, wen, be, data signals are tied to 0.


Quote:- What are the limits of the number of ports for both the core style variant as well as the HWPE variant?

I am not sure if I understand this question; in PULPissimo specifically it does not make much sense to have more then four ports without making more changes, because there are only four memory banks (so more ports would not change the available bandwidth). In PULP (multi-core cluster) there is no such limitation, although up to now we stuck with 4 ports due to other architectural considerations (mainly, to keep the size/complexity  of the interconnect under check).
Reply


Messages In This Thread
RE: Understanding the TCDM interconnect and implementing HWPEs - by fconti - 10-24-2019, 09:23 PM

Forum Jump:


Users browsing this thread: 1 Guest(s)