Adding custom instructions into RI5CY core
#2
(09-25-2020, 09:04 AM)plumerai Wrote: We are currently evaluating the RI5CY core for our project and the possibility of adding custom instructions is important for us. Some other cores (Sifive E31, Vexriscv) have simple and documented ways to do this, but I couldn't find the information about RI5CY. HWPEs are great but we may need a true custom instruction support for our needs.

RI5CY (now CV32E40P from OpenHW group) is a core with a large number of custom instructions in it. This could be an issue for you, since some of the reserved encoding space is already occupied, the core is larger to support these extensions, and there is quite a bit of performance related enhancements in the core that make adding things not as straightforward when compared to a simpler core.  

There is a fundamental difference between cores written in a higher level language (Spinal-HDL, Chisel) and directly in HDL for such additions. HDL gives you more control but asks that you do more. This also depends on your current environment and background. For someone familiar with HDL design and computer architecture, adding instructions should not be too much of an issue. What is more complex is to add the support to the development environment to support these instructions.

I would also suggest maybe to consider using a simpler core to start with. From the PULP family, I would suggest Ibex from LowRISC
  https://github.com/lowRISC/ibex
 
There are many cases, where accelerators (rather than custom instructions in the core) perform much better. This actually requires an architecture (and not really the core) that supports such operation. PULPissimo architecture has some very practical solutions to add accelerators (like HWPE)..  just saying.. 

KGF
Visit pulp-platform.org and follow us on twitter @pulp_platform
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RE: Adding custom instructions into RI5CY core - by kgf - 09-25-2020, 09:25 AM

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