Adding custom instructions into RI5CY core
#1
We are currently evaluating the RI5CY core for our project and the possibility of adding custom instructions is important for us. Some other cores (Sifive E31, Vexriscv) have simple and documented ways to do this, but I couldn't find the information about RI5CY. HWPEs are great but we may need a true custom instruction support for our needs.
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#2
(09-25-2020, 09:04 AM)plumerai Wrote: We are currently evaluating the RI5CY core for our project and the possibility of adding custom instructions is important for us. Some other cores (Sifive E31, Vexriscv) have simple and documented ways to do this, but I couldn't find the information about RI5CY. HWPEs are great but we may need a true custom instruction support for our needs.

RI5CY (now CV32E40P from OpenHW group) is a core with a large number of custom instructions in it. This could be an issue for you, since some of the reserved encoding space is already occupied, the core is larger to support these extensions, and there is quite a bit of performance related enhancements in the core that make adding things not as straightforward when compared to a simpler core.  

There is a fundamental difference between cores written in a higher level language (Spinal-HDL, Chisel) and directly in HDL for such additions. HDL gives you more control but asks that you do more. This also depends on your current environment and background. For someone familiar with HDL design and computer architecture, adding instructions should not be too much of an issue. What is more complex is to add the support to the development environment to support these instructions.

I would also suggest maybe to consider using a simpler core to start with. From the PULP family, I would suggest Ibex from LowRISC
  https://github.com/lowRISC/ibex
 
There are many cases, where accelerators (rather than custom instructions in the core) perform much better. This actually requires an architecture (and not really the core) that supports such operation. PULPissimo architecture has some very practical solutions to add accelerators (like HWPE)..  just saying.. 

KGF
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#3
We need RI5CY (or CV32E40P) extensions like bit manipulation and HW loops, and Ibex doesn't have a custom istruction interface anyway. I totally understand the benefits of the HWPEs, but still for some tasks it's good to have a custom instruction with very low latency (cycles). Does it mean that the only way to customize RI5CY is to modify the existing source codes? We are comfortable with HDL but the lack of code documentation may be an issue.
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#4
(09-25-2020, 10:17 AM)plumerai Wrote: We need RI5CY (or CV32E40P) extensions like bit manipulation and HW loops, and Ibex doesn't have a custom istruction interface anyway. I totally understand the benefits of the HWPEs, but still for some tasks it's good to have a custom instruction with very low latency (cycles). Does it mean that the only way to customize RI5CY is to modify the existing source codes? We are comfortable with HDL but the lack of code documentation may be an issue.

Note that, RI5CY is now being maintained by the OpenHW group. They are putting a lot of effort in the documentation, see under:
  https://core-v-docs-verif-strat.readthed...en/latest/

and it will only get better. Adding instructions is not really that difficult, but I admit we do not have a document ready that gives a "Adding custom instructions 101" type of tutorial. A lot of it also has to do with what kind of execution you are looking for (is it data, control, mixed) what kind of latency does it have, how does it map to existing execution units.. etc.. 

Higher level descriptions do not have implementation details like this set, so it allows you to move more quickly. But you pay the price with less control of what is going on.. There are several cases where the high-level approach is actually more efficient. Especially if you are doing a design space exploration, what if analyses etc..
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#5
Thank you very much for this clarification. We will study the docs and the core more closely.

We are interested in enhanced bit manipulation and SIMD instructions. like fused xnor-popcount-add so our needs are not very different from what has been already implemented.
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