Hello everyone,
Could someone please help me bypass the FLL logic ? I want to use an external clock for my design.
At the moment, I have removed the gf22_FLL instances and tried to connect soc_clk and per_clk directly to ref_clk.
Could anyone please share their experience of bypassing the FLL ? How did you handle the rest of the logic present in soc_clk_rst_gen.sv file ?
With this, I get error captured in the attachment.
Cheers
Could someone please help me bypass the FLL logic ? I want to use an external clock for my design.
At the moment, I have removed the gf22_FLL instances and tried to connect soc_clk and per_clk directly to ref_clk.
Could anyone please share their experience of bypassing the FLL ? How did you handle the rest of the logic present in soc_clk_rst_gen.sv file ?
With this, I get error captured in the attachment.
Cheers