02-06-2023, 02:00 PM
(06-03-2022, 07:23 PM)ivanhira Wrote: Hi,Hii,
I'm having the same problem of trying to disable the FLLs. I think my situation is the same as in this thread but I'll explain it just to be sure.
I'm trying to disable the FLLs so that I can use external clocks for the core and peripheral domains. I created two more PADs to input clocks and assigned them to the outputs in the soc_clk_rst_gen.sv module. I used the same frequency used in the normal configuration, but as soon as I comment the FLLs the simulation just runs and the program doesn't work.
I tried with the hello example and after the "Waiting for end of computation" I don't see the signal on the PADs nor in the transcript (btw I used argument io=uart when running the simulation so I should see it in the PADs too). The simulation also doesn't break, it just runs even faster as if there is nothing to really compute.
I tried to edit the init.c file in pulp-sdk, but I'm not sure how to build the sdk, because if I ran "make build-pulp-sdk" in the top directory it would clone the pulp-sdk folder overwriting the init.c file changes right? And I tried running the "make build" command as I'm not sure if it would apply the changes in the SDK, but it didn't solve the problem.
Am I missing something on how to properly build the SDK?
Thanks in advance.
I managed to get it running with the simple runtime.
You have to :
1.- comment out the fll modules and rst gen modules.
2.- set the select port of the clock muxes in the soc_clk_rst_gen module to "1" (this is the same as setting peripheral, core and cluster clocks to ref_clock).
3.- comment out the pos_init function in init.c (this function sets the target frequencies of the FLLs, if you call it, the system will stall till specified frequency is achieved).
I hope this helps ^^
Good luck