[Vivado] behavioural simulation won't start

[LarsKeuninckx]

I have exactly the same problem, when compiling for the nexysA7-100T board:

Use nexys4DDR/A7 constraints.
# synth_design -rtl -name rtl_1 -sfcu;
Command: synth_design -rtl -name rtl_1 -sfcu
Starting synth_design
Using part: xc7a100tcsg324-1
Top: xilinx_pulpissimo
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
WARNING: [Synth 8-1921] elaboration system task error violates IEEE 1800 syntax [/home/lars/Argus/pulpissimo/ips/pulp_soc/rtl/components/apb_soc_ctrl.sv:137]
WARNING: [Synth 8-2507] parameter declaration becomes local in hwpe_stream_merge with formal parameter declaration list [/home/lars/Argus/pulpissimo/ips/hwpe-stream/rtl/hwpe_stream_merge.sv:31]
WARNING: [Synth 8-2507] parameter declaration becomes local in hwpe_stream_split with formal parameter declaration list [/home/lars/Argus/pulpissimo/ips/hwpe-stream/rtl/hwpe_stream_split.sv:31]
WARNING: [Synth 8-2507] parameter declaration becomes local in hwpe_stream_split with formal parameter declaration list [/home/lars/Argus/pulpissimo/ips/hwpe-stream/rtl/hwpe_stream_split.sv:32]
WARNING: [Synth 8-1921] elaboration system task error violates IEEE 1800 syntax [/home/lars/Argus/pulpissimo/ips/pulp_soc/rtl/pulp_soc/interleaved_crossbar.sv:48]
WARNING: [Synth 8-1921] elaboration system task error violates IEEE 1800 syntax [/home/lars/Argus/pulpissimo/rtl/pulpissimo/pad_control.sv:197]
WARNING: [Synth 8-1921] elaboration system task error violates IEEE 1800 syntax [/home/lars/Argus/pulpissimo/rtl/pulpissimo/pad_control.sv:198]
WARNING: [Synth 8-1921] elaboration system task error violates IEEE 1800 syntax [/home/lars/Argus/pulpissimo/rtl/pulpissimo/pad_control.sv:199]
WARNING: [Synth 8-2490] overwriting previous definition of module pulp_clock_mux2 [/home/lars/Argus/pulpissimo/ips/tech_cells_generic/src/deprecated/pulp_clk_cells_xilinx.sv:53]
WARNING: [Synth 8-2490] overwriting previous definition of module pulp_clock_gating [/home/lars/Argus/pulpissimo/fpga/pulpissimo-nexys/rtl/pulp_clock_gating_xilinx.sv:11]
ERROR: [Synth 8-1587] an enum variable may only be assigned to same enum typed variable or one of its values [/home/lars/Argus/pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv:445]
INFO: [Synth 8-2350] module riscv_ex_stage ignored due to previous errors [/home/lars/Argus/pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv:40]
Failed to read verilog '/home/lars/Argus/pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv'
2 Infos, 10 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details
INFO: [Common 17-206] Exiting Vivado at Wed Jan 6 11:08:05 2021...
Makefile:11: recipe for target 'all' failed
make[1]: *** [all] Error 1
make[1]: Leaving directory '/home/lars/Argus/pulpissimo/fpga/pulpissimo-nexys'
Makefile:41: recipe for target 'nexys' failed

Does anyone know how to solve this?